Touch and Cross Router. - Kaoru Kawamura; Tatsuya Shindo; Toshiyuki Shibuya; Hideki Miwatari; Yoshie Ohki (ICCAD, 1990)

Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. - Jason Cong; Honching Peter Li; Sung Kyu Lim; Toshiyuki Shibuya; Dongmin Xu (ICCAD, 1997)

PDL: A New Physical Synthesis Methodology. - Toshiyuki Shibuya; Rajeev Murgai; Tadashi Konno; Kazuhiro Emi; Kaoru Kawamura (ISQED, 2003)

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? - Chung-Kuan Cheng; Steve Lin; Andrew B. Kahng; Keh-Jeng Chang; Vijay Pitchumani; Toshiyuki Shibuya; Roberto Suaya; Zhiping Yu; Fook-Luen Heng; Don MacMillen (ASP-DAC, 2005)

Fast power network analysis with multiple clock domains. - Wanping Zhang; Ling Zhang; Rui Shi 003; He Peng; Zhi Zhu; Lew Chua-Eoan; Rajeev Murgai; Toshiyuki Shibuya; Noriyuki Ito; Chung-Kuan Cheng (ICCD, 2007)

Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis. - Katsumi Homma; Izumi Nitta; Toshiyuki Shibuya (ASP-DAC, 2008)

Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. - Wanping Zhang; Yi Zhu 002; Wenjian Yu; Ling Zhang; Rui Shi 003; He Peng; Zhi Zhu; Lew Chua-Eoan; Rajeev Murgai; Toshiyuki Shibuya; Nuriyoki Ito; Chung-Kuan Cheng (DATE, 2008)

Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit. - Yu Liu; Masato Yoshioka; Katsumi Homma; Toshiyuki Shibuya (ASP-DAC, 2009)

Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality. - Yu Liu; Masato Yoshioka; Katsumi Homma; Toshiyuki Shibuya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Efficient Power Network Analysis Considering Multidomain Clock Gating. - Wanping Zhang; Wenjian Yu; Xiang Hu; Ling Zhang; Rui Shi 003; He Peng; Zhi Zhu; Lew Chua-Eoan; Rajeev Murgai; Toshiyuki Shibuya; Noriyuki Ito; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances. - Yu Liu; Masato Yoshioka; Katsumi Homma; Toshiyuki Shibuya; Yuzi Kanazawa (DAC, 2010)

B-escape: a simultaneous escape routing algorithm based on boundary routing. - Lijuan Luo; Tan Yan; Qiang Ma 002; Martin D. F. Wong; Toshiyuki Shibuya (ISPD, 2010)

"Condition-based" dummy fill insertion method based on ECP and CMP predictive models. - Izumi Nitta; Yuji Kanazawa; Daisuke Fukuda; Toshiyuki Shibuya; Naoki Idani; Masaru Ito; Osamu Yamasaki; Norihiro Harada; Takanori Hiramoto (ISQED, 2010)

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. - Yasuo Hidaka; Takeshi Horie; Yoichi Koyanagi; Takashi Miyoshi; Hideki Osone; Samir Parikh; Subodh M. Reddy; Toshiyuki Shibuya; Yasushi Umezawa; William W. Walker (ISSCC, 2011)

A New Strategy for Simultaneous Escape Based on Boundary Routing. - Lijuan Luo; Tan Yan; Qiang Ma 002; Martin D. F. Wong; Toshiyuki Shibuya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. - Samir Parikh; Tony Kao; Yasuo Hidaka; Jian Jiang; Asako Toda; Scott McLeod; William W. Walker; Yoichi Koyanagi; Toshiyuki Shibuya; Jun Yamada (ISSCC, 2013)

Conference Reports: Recap of the 24th Asia and South Pacific Design Automation Conference. - Toshiyuki Shibuya (IEEE Des. Test, 2019)

Foreword. - Toshiyuki Shibuya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)