Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond. - Noriaki Oda; Hiroyuki Kunishima; Takashi Kyouno; Kazuhiro Takeda; Tomoaki Tanaka; Toshiyuki Takewaki; Masahiro Ikeda (IEICE Trans. Electron., 2006)

Accurate Modeling Method for Cu Interconnect. - Kenta Yamada; Hiroshi Kitahara; Yoshihiko Asai; Hideo Sakamoto; Norio Okada; Makoto Yasuda; Noriaki Oda; Michio Sakurai; Masayuki Hiroi; Toshiyuki Takewaki; Sadayuki Ohnishi; Manabu Iguchi 002; et al. (IEICE Trans. Electron., 2008)