Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. - Takashi Kawanami; Masakazu Hioki; Hiroshi Nagase; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPGA, 2004)

Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity. - Takashi Kawanami; Masakazu Hioki; Hiroshi Nagase; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (IEICE Trans. Inf. Syst., 2004)

Evaluation of granularity on threshold voltage control in flex power FPGA. - Masakazu Hioki; Takashi Kawanami; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPT, 2006)

Optimal set of body bias voltages for an FPGA with field-programmable Vth components. - Takashi Kawanami; Masakazu Hioki; Yohei Matsumoto; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPT, 2006)

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Shuhei Kadoyama; Takashi Aikyo; Yuzo Takamatsu; Koji Yamazaki; Toshiyuki Tsutsumi; Hiroyuki Yotsuyanagi; Masaki Hashizume (ATS, 2007)

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. - Yohei Matsumoto; Masakazu Hioki; Takashi Kawanami; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPGA, 2007)

A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip. - Masakazu Hioki; Takashi Kawanami; Yohei Matsumoto; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike; Toshiyuki Tsutsumi (FPT, 2007)

Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. - Takashi Kawanami; Masakazu Hioki; Yohei Matsumoto; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (IEICE Trans. Inf. Syst., 2007)

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. - Yohei Matsumoto; Masakazu Hioki; Takashi Kawanami; Hanpei Koike; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa (ACM Trans. Reconfigurable Technol. Syst., 2008)

New Class of Tests for Open Faults with Considering Adjacent Lines. - Hiroshi Takahashi; Yoshinobu Higami; Yuzo Takamatsu; Koji Yamazaki; Toshiyuki Tsutsumi; Hiroyuki Yotsuyanagi; Masaki Hashizume (Asian Test Symposium, 2009)

A Novel Approach for Improving the Quality of Open Fault Diagnosis. - Koji Yamazaki; Toshiyuki Tsutsumi; Hiroshi Takahashi; Yoshinobu Higami; Takashi Aikyo; Yuzo Takamatsu; Hiroyuki Yotsuyanagi; Masaki Hashizume (VLSI Design, 2009)

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. - Hiroyuki Yotsuyanagi; Masaki Hashizume; Toshiyuki Tsutsumi; Koji Yamazaki; Takashi Aikyo; Yoshinobu Higami; Hiroshi Takahashi; Yuzo Takamatsu (VLSI Design, 2009)

Development of Pipeline Time Chart Too for Microprocessor Design Education. - Tomoyuki Morimoto; Toshiyuki Tsutsumi (ICCE, 2010)

Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. - Koji Yamazaki; Toshiyuki Tsutsumi; Hiroshi Takahashi; Yoshinobu Higami; Hironobu Yotsuyanagi; Masaki Hashizume; Kewal K. Saluja (Asian Test Symposium, 2013)

Fully-functional FPGA prototype with fine-grain programmable body biasing. - Masakazu Hioki; Toshihiro Sekigawa; Tadashi Nakagawa; Hanpei Koike; Yohei Matsumoto; Takashi Kawanami; Toshiyuki Tsutsumi (FPGA, 2013)

Impacts of flexible Vth control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs. - Yasuhiro Ogasahara; Tadashi Nakagawa; Toshihiro Sekigawa; Toshiyuki Tsutsumi; Hanpei Koike (IEICE Electron. Express, 2015)

Early Development of Visualization Tool for Instruction Implement of Microprocessor. - Tomoyuki Morimoto; Ryouhei Iwamoto; Toshiyuki Tsutsumi (ISCIT, 2019)

Visualization Tool of Microprocessor Instruction for Designing New Architecture with Meta-Instructions. - Tomoyuki Morimoto; Shunsuke Onogi; Tadahiro Ogita; Ryota Kawamata; Ziming Wang; Toshiyuki Tsutsumi (ISCIT, 2022)

Initial Implementation and Utilization of Instruction Dynamic Simulation in MEIMAT. - Tadahiro Ogita; Tomoyuki Morimoto; Shunsuke Onogi; Ryota Kawamata; Ziming Wang; Toshiyuki Tsutsumi (ISCIT, 2022)

Microprocessor Instruction Design Tool for RISC-V Architecture. - Jiahui Luo; Tomoyuki Morimoto; Tadahiro Ogita; Ryota Kawamata; Zi-Ming Wang; Toshiyuki Tsutsumi (ISCIT, 2023)

Visualization and Simulation of Any MPU Architecture Design with Meta-Instruction. - Tomoyuki Morimoto; Ziming Wang; Jiahui Luo; Sota Ogawa; Toshiyuki Tsutsumi (ISCIT, 2024)