Dynamic phase-based tuning for embedded systems using phase distance mapping. - Tosiron Adegbija; Ann Gordon-Ross; Arslan Munir (ICCD, 2012)

Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems. - Tosiron Adegbija; Ann Gordon-Ross (ICCD, 2013)

Thermal-aware phase-based tuning of embedded systems. - Tosiron Adegbija; Ann Gordon-Ross (ACM Great Lakes Symposium on VLSI, 2014)

Analysis of cache tuner architectural layouts for multicore embedded systems. - Tosiron Adegbija; Ann Gordon-Ross; Marisha Rawlins (IPCCC, 2014)

Dynamic Phase-Based Optimization of Embedded Systems. - Tosiron Adegbija; Ann Gordon-Ross (ISVLSI, 2014)

Phase distance mapping: a phase-based cache tuning methodology for embedded systems. - Tosiron Adegbija; Ann Gordon-Ross; Arslan Munir (Des. Autom. Embed. Syst., 2014)

Phase-based Cache Locking for Embedded Systems. - Tosiron Adegbija; Ann Gordon-Ross (ACM Great Lakes Symposium on VLSI, 2015)

Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems. - Tosiron Adegbija (ACM Great Lakes Symposium on VLSI, 2016)

Phase-Based Dynamic Instruction Window Optimization for Embedded Systems. - Tosiron Adegbija; Ann Gordon-Ross (ISVLSI, 2016)

Temperature-aware Dynamic Optimization of Embedded Systems. - Tosiron Adegbija; Ann Gordon-Ross (CoRR, 2016)

Microprocessor Optimizations for the Internet of Things. - Tosiron Adegbija; Anita Rogacs; Chandrakant Patel; Ann Gordon-Ross (CoRR, 2016)

Application-Specific Autonomic Cache Tuning for General Purpose GPUs. - Sam Gianelli; Edward Richter; Diego Jiménez; Hugo Valdez; Tosiron Adegbija; Ali Akoglu (ICCAC, 2017)

Coding for Efficient Caching in Multicore Embedded Systems. - Tosiron Adegbija; Ravi Tandon (ISVLSI, 2017)

Exploiting Configurability as a Defense against Cache Side Channel Attacks. - Chenxi Dai; Tosiron Adegbija (ISVLSI, 2017)

PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems. - Sam Gianelli; Tosiron Adegbija (ISVLSI, 2017)

A Workload Characterization for the Internet of Medical Things (IoMT). - Ankur Limaye; Tosiron Adegbija (ISVLSI, 2017)

AMELIA: An application of the Internet of Things for aviation safety. - Jeremiah Pate; Tosiron Adegbija (CCNC, 2018)

LARS: Logically adaptable retention time STT-RAM cache for embedded systems. - Kyle Kuan; Tosiron Adegbija (DATE, 2018)

TaSaT: Thermal-Aware Scheduling and Tuning Algorithm for Heterogeneous and Configurable Embedded Systems. - Mohamad Hammam Alsafrjalani; Tosiron Adegbija (ACM Great Lakes Symposium on VLSI, 2018)

A Workload Characterization of the SPEC CPU2017 Benchmark Suite. - Ankur Limaye; Tosiron Adegbija (ISPASS, 2018)

Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges. - Islam Badreldin; Ann Gordon-Ross; Tosiron Adegbija; Mohamad Hammam Alsafrjalani (ISVLSI, 2018)

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems. - Tosiron Adegbija; Ann Gordon-Ross (Comput., 2018)

HERMIT: A Benchmark Suite for the Internet of Medical Things. - Ankur Limaye; Tosiron Adegbija (IEEE Internet Things J., 2018)

Microprocessor Optimizations for the Internet of Things: A Survey. - Tosiron Adegbija; Anita Rogacs; Chandrakant Patel; Ann Gordon-Ross (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking. - Tosiron Adegbija; Ann Gordon-Ross (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Right-Provisioned IoT Edge Computing: An Overview. - Tosiron Adegbija; Roman Lysecky; Vinu Vijay Kumar (ACM Great Lakes Symposium on VLSI, 2019)

MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache. - Kyle Kuan; Tosiron Adegbija (ACM Great Lakes Symposium on VLSI, 2019)

SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. - Dhruv Gajaria; Kyle Kuan; Tosiron Adegbija (IGSC, 2019)

Bit-Wise and Multi-GPU Implementations of the DNA Recombination Algorithm. - Elnaz Tavakoli Yazdi; Ankur Limaye; Ali Akoglu; Tosiron Adegbija; Adam Buntzman (HiPC, 2019)

Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems. - Mohamad Hammam Alsafrjalani; Tosiron Adegbija; Lokesh Ramamoorthi (ISQED, 2019)

Energy and Performance Analysis of STTRAM Caches for Mobile Applications. - Kyle Kuan; Tosiron Adegbija (MCSoC, 2019)

ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors. - Dhruv Gajaria; Tosiron Adegbija (MEMSYS, 2019)

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. - Kyle Kuan; Tosiron Adegbija (IEEE Trans. Computers, 2019)

A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. - Kyle Kuan; Tosiron Adegbija (ICCD, 2020)

Message from the Technical Program Chairs iSES 2020. - Yasuhiro Takahashi; Tosiron Adegbija; Linga Reddy Cenkeramaddi (iSES, 2020)

CONDENSE: A Moving Target Defense Approach for Mitigating Cache Side-Channel Attacks. - Chenxi Dai; Tosiron Adegbija (IEEE Consumer Electron. Mag., 2020)

ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture. - Renato Cordeiro; Dhruv Gajaria; Ankur Limaye; Tosiron Adegbija; Nima Karimian; Fatemeh Tehranipoor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. - Kyle Kuan; Tosiron Adegbija (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior. - Keeley Criswell; Tosiron Adegbija (IEEE Trans. Parallel Distributed Syst., 2020)

DOSAGE: Generating Domain-Specific Accelerators for Resource-Constrained Computing. - Ankur Limaye; Tosiron Adegbija (ISLPED, 2021)

Energy characterization of graph workloads. - Ankur Limaye; Antonino Tumeo; Tosiron Adegbija (Sustain. Comput. Informatics Syst., 2021)

A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy. - Dhruv Gajaria; Kevin Antony Gomez; Tosiron Adegbija (ICCD, 2022)

A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation. - Kyle Kuan; Tosiron Adegbija (ISVLSI, 2022)

Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads. - Dhruv Gajaria; Tosiron Adegbija (Future Gener. Comput. Syst., 2022)

A high-level synthesis approach for precisely-timed, energy-efficient embedded systems. - Yuchao Liao; Tosiron Adegbija; Roman Lysecky (Sustain. Comput. Informatics Syst., 2022)

Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing. - Dhruv Gajaria; Tosiron Adegbija (J. Signal Process. Syst., 2022)

Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning. - Yuchao Liao; Tosiron Adegbija; Roman Lysecky (ASP-DAC, 2023)

Jazznet: A Dataset of Fundamental Piano Patterns for Music Audio Machine Learning Research. - Tosiron Adegbija (ICASSP, 2023)

Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators. - Ilkin Aliyev; Kama Svoboda; Tosiron Adegbija (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing. - Dhruv Gajaria; Tosiron Adegbija; Kevin Antony Gomez (ASAP, 2024)

Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks. - Ilkin Aliyev; Tosiron Adegbija (DATE, 2024)

Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning. - Yuchao Liao; Tosiron Adegbija; Roman Lysecky; Ravi Tandon (ACM Great Lakes Symposium on VLSI, 2024)

Are LLMs Any Good for High-Level Synthesis? - Yuchao Liao; Tosiron Adegbija; Roman Lysecky (ICCAD, 2024)

PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine. - Ilkin Aliyev; Tosiron Adegbija (ISCAS, 2024)

Message from the Technical Program Chairs; ISVLSI 2024. - Garrett S. Rose; Tosiron Adegbija; Selçuk Köse (ISVLSI, 2024)

Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview. - Ilkin Aliyev; Kama Svoboda; Tosiron Adegbija; Jean-Marc Fellous (MCSoC, 2024)

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey. - Alaba Yusuf; Tosiron Adegbija; Dhruv Gajaria (IEEE Access, 2024)

Deep Inverse Design for High-Level Synthesis. - Ping Chang; Tosiron Adegbija; Yuchao Liao; Claudio Talarico; Ao Li 004; Janet Roveda (CoRR, 2024)

An Open-Source Tool for Generating Domain-Specific Accelerators for Resource-Constrained Computing. - David T. Kerns; Tosiron Adegbija (J. Open Source Softw., 2024)

STT-RAM-Based Hierarchical in-Memory Computing. - Dhruv Gajaria; Kevin Antony Gomez; Tosiron Adegbija (IEEE Trans. Parallel Distributed Syst., 2024)

Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture. - Ilkin Aliyev; Jesus Lopez; Tosiron Adegbija (DATE, 2025)

System-Level Design Space Exploration for High-Level Synthesis Under End-to-End Latency Constraints. - Yuchao Liao; Tosiron Adegbija; Roman Lysecky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Guest Editorial: Selected Papers From IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024. - Himanshu Thapliyal; Jürgen Becker 001; Garrett S. Rose; Tosiron Adegbija; Selçuk Köse (IEEE Trans. Very Large Scale Integr. Syst., 2025)