A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100. - Tom Shimizu; Toyohiko Yoshida; Yuichi Saito; Masahito Matsuo; Tatsuya Enomoto (COMPCON, 1988)

A 32-bit microprocessor with high performance bit-map manipulation instructions. - Toru Shimizu; Shunichi Iwata; Yuichi Saito; Toyohiko Yoshida; Masahito Matsuo; Junichi Hinata; Kazunori Saito (ICCD, 1989)

A strategy for avoiding pipeline interlock delays in a microprocessor. - Toyohiko Yoshida; Masahito Matsuo; Tatsuya Ueda; Yuichi Saito (ICCD, 1990)

The Gmicro/100 32-bit microprocessor. - Toyohiko Yoshida; Toru Shimisu; Shigeo Mizugaki; Jun-ichi Hinata (IEEE Micro, 1991)

A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface. - Masahito Matsuo; Hiroyuki Kondo; Yukari Takata; Souichi Kobayashi; Mitsugu Satoh; Toyohiko Yoshida; Yuichi Saito; Jun-ichi Hinata (ICCD, 1994)

Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor. - Mamoru Sakamoto; Toyohiko Yoshida; Yasuhiro Nunomura; Yukihiko Shimazu (ICCD, 1996)

A dual-issue RISC processor for multimedia signal processing. - Hisakazu Sato; Edgar Holmann; Toyohiko Yoshida; Masahito Matsuo; Toru Kengaku (ICASSP, 1997)

A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications. - Atsuo Hanami; Stefan Scotzniovsky; Kazuya Ishihara; Tetsuya Matsumura; Shin'ichi Takeuchi; Haruyuki Ohkuma; Koji Nishigaki; Hirokazu Suzuki; Masahiro Kazayama; Toyohiko Yoshida; Koji Tsuchihashi (CICC, 1998)

Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding. - Edgar Holmann; Toyohiko Yoshida; Akira Yamada 005; Shin-ichi Uramoto (J. VLSI Signal Process., 1998)

A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores. - Satoshi Kumaki; Tetsuya Matsumura; Kamya Ishihara; Hiroshi Segawa; Kiyofumi Kawamoto; Hideo Ohira; Toshiaki Shimada; Hidenori Sato; Takashi Hattori; Tetsuro Wada; Hiroshi Honma; Tetsuya Watanabe; et al. (CICC, 1999)

Evaluation of processor code efficiency for embedded systems. - Morgan Hirosuke Miki; Mamoru Sakamoto; Shingo Miyamoto; Yoshinori Takeuchi; Toyohiko Yoshida; Isao Shirakawa (ICS, 2001)

Code Efficiency Evaluation for Embedded Processors. - Morgan Hirosuke Miki; Mamoru Sakamoto; Shingo Miyamoto; Yoshinori Takeuchi; Toyohiko Yoshida; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)