A BIST approach for very deep sub-micron (VDSM) defects. - Yasuo Sato; Toyohito Ikeya; Michinobu Nakao; Takaharu Nagumo (ITC, 2000)

A Practical Logic BIST for ASIC Designs. - Yasuo Sato; Motoyuki Sato; Koki Tsutsumida; Toyohito Ikeya; Masatoshi Kawashima (Asian Test Symposium, 2001)

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process. - Masafumi Onouchi; Kazuo Otsuga; Yasuto Igarashi; Toyohito Ikeya; Sadayuki Morita; Koichiro Ishibashi; Kazumasa Yanagisawa (A-SSCC, 2011)

An on-chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage sensor. - Kazuo Otsuga; Masafumi Onouchi; Yasuto Igarashi; Toyohito Ikeya; Sadayuki Morita; Koichiro Ishibashi; Kazumasa Yanagisawa (SoCC, 2012)