Efficient design of full adder and subtractor using 5-input majority gate in QCA. - Ramanand Jaiswal; Trailokya Nath Sasamal (IC3, 2017)

An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata. - Ashvin Chudasama; Trailokya Nath Sasamal; Jyoti Yadav (Comput. Electr. Eng., 2018)

Efficient design of coplanar ripple carry adder in QCA. - Trailokya Nath Sasamal; Ashutosh Kumar Singh 001; Umesh Ghanekar (IET Circuits Devices Syst., 2018)

Efficient Design of Reversible Logic ALU Using Coplanar Quantum-Dot Cellular Automata. - Trailokya Nath Sasamal; Anand Mohan; Ashutosh Kumar Singh 001 (J. Circuits Syst. Comput., 2018)

Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates. - Trailokya Nath Sasamal; Ashutosh Kumar Singh 001; Umesh Ghanekar (J. Circuits Syst. Comput., 2019)

Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective - Trailokya Nath Sasamal; Ashutosh Kumar Singh 001; Anand Mohan (Springer, 2020)

High Speed Comparator and Parity generator in QCA based on optimal XOR structure. - Trailokya Nath Sasamal; Gaurav Saini; Vineet Jaiswal (RTSI, 2022)

Guest editorial: Introduction to the special section on recent advances and challenges in quantum-dot cellular automata (VSI-QCA). - Ashutosh Kumar Singh 001; Trailokya Nath Sasamal; Lau Siong Hoe; P. W. Chandana Prasad; Saeed Rasouli Heikalabad (Comput. Electr. Eng., 2022)

Novel approach for the design of efficient full adder in MQCA. - Vineet Jaiswal; Trailokya Nath Sasamal (J. Supercomput., 2023)

A Novel Approach to Design Multiplexer Using Magnetic Quantum-Dot Cellular Automata. - Vineet Jaiswal; Trailokya Nath Sasamal (IEEE Embed. Syst. Lett., 2023)

Placement and routing approach for MQCA-based designs with BFS and A* algorithms. - Vineet Jaiswal; Trailokya Nath Sasamal (Comput. Electr. Eng., 2024)