Embedded LO synthesis method in harmonic rejection mixers. - Travis Forbes; Ranjit Gharpurey (MWSCAS, 2012)

A frequency-folded ADC architecture with digital LO synthesis. - Travis Forbes; Wei-Gi Ho; Nan Sun 003; Ranjit Gharpurey (ISCAS, 2013)

An active interference cancellation technique with harmonic rejection for a broadband channelizer. - Wei-Gi Ho; Travis Forbes; Vineet Kumar Singh; Ranjit Gharpurey (MWSCAS, 2013)

Design and Analysis of Harmonic Rejection Mixers With Programmable LO Frequency. - Travis Forbes; Wei-Gi Ho; Ranjit Gharpurey (IEEE J. Solid State Circuits, 2013)

A 16-band channelizer employing harmonic rejection mixers with enhanced image rejection. - Vineet Kumar Singh; Travis Forbes; Wei-Gi Ho; Jaegan Ko; Ranjit Gharpurey (CICC, 2014)

A 2 GS/s Frequency-Folded ADC-Based Broadband Sampling Receiver. - Travis Forbes; Ranjit Gharpurey (IEEE J. Solid State Circuits, 2014)

A low-power two-stage harmonic rejection quadrature mixer employing bias-current reuse. - Wei-Gi Ho; Travis Forbes; Ranjit Gharpurey (MWSCAS, 2015)

A 0.2-2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55-448.6 ns Programmable Delay Range and 330 ns/mm2 Area Efficiency. - Travis Forbes; Benjamin Magstadt; Jesse Moody; Justine Saugen; Andrew Suchanek; Spencer Nelson (IEEE J. Solid State Circuits, 2023)

25.4 A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz. - Jesse Moody; Tyler Liebsch; Patrick Finnegan; Stefan Lepkowski; Robert Costanzo; Mieko Hirabayashi; Matt Jordan; Travis Forbes; Christopher Nordquist (ISSCC, 2025)