Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis. - Adam Arnesen; Kevin Ellsworth; Derrick Gibelyou; Travis Haroldsen; Jared Havican; Marc Padilla; Brent E. Nelson; Michael Rice; Michael J. Wirthlin (FPL, 2010)

Rapid FPGA design prototyping through preservation of system logic: A case study. - Travis Haroldsen; Brent E. Nelson; Brad White (FPL, 2013)

RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs. - Travis Haroldsen; Brent E. Nelson; Brad L. Hutchings (FPGA, 2015)

Packing a modern Xilinx FPGA using RapidSmith. - Travis Haroldsen; Brent E. Nelson; Brad L. Hutchings (ReConFig, 2016)