High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM Network. - Tresa Joseph; T. S. Bindiya (VDAT, 2021)

Performance-Driven LSTM Accelerator Hardware Using Split-Matrix-Based MVM. - Tresa Joseph; T. S. Bindiya (Circuits Syst. Signal Process., 2023)

Power and Delay-Efficient Matrix Vector Multiplier Units for the LSTM Networks Using Activity Span Reduction Technique and Recursive Adders. - Tresa Joseph; T. S. Bindiya (Circuits Syst. Signal Process., 2023)

Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions. - Tresa Joseph; T. S. Bindiya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI. - Mrinmay Sasmal; Tresa Joseph; T. S. Bindiya (IEEE Comput. Archit. Lett., 2024)