The design of peak constrained least squares FIR filters with low complexity finite precision coefficients. - Trevor W. Fox; Laurence E. Turner (ISCAS (2), 2001)

A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM. - Alex Carreira; Trevor W. Fox; Laurence E. Turner (FPL, 2002)

Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. - Trevor W. Fox; Laurence E. Turner (FPL, 2002)

A method of implementing bit-serial LDI ladder filters in FPGAs using JBits. - Alex Carreira; Trevor W. Fox; Laurence E. Turner (FPT, 2002)

Low coefficient complexity approximations of the one dimensional discrete cosine transform. - Trevor W. Fox; Laurence E. Turner (ISCAS (1), 2002)

The Multiplier Tree FIR filter architecture. - Alex Carreira; Trevor W. Fox (FPT, 2003)

The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks. - Trevor W. Fox; Alex Carreira; Laurence E. Turner (IWSOC, 2003)

A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs. - Alex Carreira; Trevor W. Fox; Laurence E. Turner (EURASIP J. Adv. Signal Process., 2003)

Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations. - Trevor W. Fox; Laurence E. Turner (EURASIP J. Adv. Signal Process., 2003)

A Digital Signal Processing Method for Gene Prediction with Improved Noise Suppression. - Trevor W. Fox; Alex Carreira (EURASIP J. Adv. Signal Process., 2004)