Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra. - Anchit Arun; Ananya Chakraborty; Priyanka Dutta 004; Debajyoti Pal; Tridibesh Nag; Debashis De; Sudip Ghosh 001; Hafizur Rahaman 001 (IAIT, 2023)