SkipCache: miss-rate aware cache management. - Kanakagiri Raghavendra; Tripti S. Warrier; Madhu Mutyam (PACT, 2012)

Way Sharing Set Associative Cache Architecture. - C. J. Janraj; T. Venkata Kalyan; Tripti S. Warrier; Madhu Mutyam (VLSI Design, 2012)

An Application-Aware Cache Replacement Policy for Last-Level Caches. - Tripti S. Warrier; B. Anupama; Madhu Mutyam (ARCS, 2013)

SAMO: store aware memory optimizations. - Kanakagiri Raghavendra; Tripti S. Warrier; Madhu Mutyam (Conf. Computing Frontiers, 2014)

SkipCache: application aware cache management for chip multi-processors. - Tripti S. Warrier; Kanakagiri Raghavendra; Madhu Mutyam (IET Comput. Digit. Tech., 2015)

2L-2D Routing for Buffered Mesh Network-on-Chip. - Rose George Kunthara; K. Neethu; Rekha K. James; Simi Zerine Sleeba; Tripti S. Warrier; John Jose (VDAT, 2019)

Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V. - P. S. Babu; Snehashri Sivaraman; Deepa N. Sarma; Tripti S. Warrier (VLSID, 2021)

True Random Number Generator based on Voltage-Gated Spintronic structure. - Alisha P. B; Tripti S. Warrier (VLSID, 2023)