Transistor Modeling for the VDSM Era. - Michael S. Shur; Tor A. Fjeldly; Trond Ytterdal (ISQED, 2000)

A mixed-signal, functional level simulation framework based on SystemC for system-on-a-chip applications. - Thomas E. Bonnerud; Bjørnar Hernes; Trond Ytterdal (CICC, 2001)

A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits. - Snorre Aunet; Yngvar Berg; Trond Ytterdal; Øivind Næss; Trond Sæther (ICECS, 2001)

Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits. - Trond Ytterdal; Snorre Aunet (ISCAS (5), 2002)

Behavioral modeling and simulation of high-speed analog-to-digital converters using SystemC. - Johnny Bjørnsen; Trond Ytterdal (ISCAS (3), 2003)

Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemC. - Jan Lundgren; Bengt Oelmann; Trond Ytterdal; Patrik Eriksson; Munir Abdalla; Mattias O'Nils (ISVLSI, 2003)

A single-ended to differential capacitive sensor interface circuit designed in CMOS technology. - Tajeshwar Singh; Trond Ytterdal (ISCAS (1), 2004)

Simplified gate level noise injection models for behavioral noise coupling simulation. - Jan Lundgren; Trond Ytterdal; Mattias O'Nils (ECCTD, 2005)

A 220mW 14b 40MSPS gain calibrated pipelined ADC. - Johnny Bjørnsen; Øystein Moldsvor; Trond Sæther; Trond Ytterdal (ESSCIRC, 2005)

Jitter analysis of general charge sampling amplifiers. - Linga Reddy Cenkeramaddi; Trond Ytterdal (ISCAS, 2006)

Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging. - Linga Reddy Cenkeramaddi; Tajeshwar Singh; Trond Ytterdal (ACM Great Lakes Symposium on VLSI, 2007)

Analog Circuit Design in Nanoscale CMOS Technologies. - Lanny L. Lewyn; Trond Ytterdal; Carsten Wulff; Kenneth W. Martin (Proc. IEEE, 2009)

Feedback Biasing in Nanoscale CMOS Technologies. - Tajeshwar Singh; Trond Sæther; Trond Ytterdal (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Resonators in Open-Loop Sigma-Delta Modulators. - Carsten Wulff; Trond Ytterdal (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Current-Mode Capacitive Sensor Interface Circuit With Single-Ended to Differential Output Capability. - Tajeshwar Singh; Trond Sæther; Trond Ytterdal (IEEE Trans. Instrum. Meas., 2009)

Figure-of-merit optimization of a low noise amplifier in 180 nm CMOS. - Hans Herman Hansen; Trond Ytterdal (ECCTD, 2011)

A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS. - Tuan Vu Cao; Snorre Aunet; Trond Ytterdal (NORCHIP, 2012)

Modeling and design of a dual-residue pipelined ADC in 130nm CMOS. - Eirik Steen-Hansen; Trond Ytterdal (NORCHIP, 2012)

Low noise front-end amplifier design for medical ultrasound imaging applications. - Surya Sharma; Trond Ytterdal (VLSI-SoC, 2012)

Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC). - Atila Alvandpour; Patrick Reynaert; Trond Ytterdal (IEEE J. Solid State Circuits, 2012)

A low-power, low-noise, and low-cost VGA for second harmonic imaging ultrasound probes. - Peng Wang 013; Trond Ytterdal; Thomas Moe Halvorsrod (BioCAS, 2013)

Low power OTA-less I-V-converter with single-ended to differential conversion for capacitive sensor interfaces. - Hourieh Attarzadeh; Trond Ytterdal (ECCTD, 2013)

A 65nm CMOS front-end LNA for medical ultrasound imaging with feedback employing noise and distortion cancellation. - Jon Håvard Eriksrod; Trond Ytterdal (ECCTD, 2013)

A low power analog RAM implementation for in-probe beamforming in ultrasound imaging. - Surya Sharma; Trond Ytterdal (ECCTD, 2013)

A low noise single-ended to differential linear charge sampling SC-VGA for second harmonic cardiac ultrasound imaging. - Peng Wang 013; Trond Ytterdal; Thomas Halvorsrod (ECCTD, 2013)

A low noise single-end to differential switched-capacitor VGA for PZT-Xducer ultrasound imaging. - Peng Wang 013; Trond Ytterdal; Thomas Halvorsrod (ECCTD, 2013)

Low power front end electronics for in-probe beamforming in ultrasound imaging. - Surya Sharma; Trond Ytterdal (NORCHIP, 2013)

A 7-bit 50ms/s single-ended asynchronous SAR ADC in 65nm CMOS. - Ye Xu; Trond Ytterdal (NORCHIP, 2013)

A Low-Noise Variable-Gain Amplifier for in-Probe 3D Imaging Applications Based on CMUT Transducers. - Hourieh Attarzadeh; Trond Ytterdal (ISVLSI, 2014)

Modular layout-friendly cell library design applied for subthreshold CMOS. - Jonathan Edvard Bjerkedok; Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (NORCHIP, 2014)

Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout. - Magne Voernes; Trond Ytterdal; Snorre Aunet (NORCHIP, 2014)

Exploiting short channel effects and multi-Vt technology for increased robustness and reduced energy consumption, with application to a 16-bit subthreshold adder implemented in 65 nm CMOS. - Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (ECCTD, 2015)

4 Sub-/near-threshold flip-flops with application to frequency dividers. - Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (ECCTD, 2015)

A differential inverter-based switched-capacitor oscillator in 65 nm CMOS technology. - Peng Wang 013; György Csaba; Wolfgang Porod; Trond Ytterdal (ECCTD, 2015)

Inverter-based Low-power, low-noise SC-VGA and 8 channel pipelined S/H analog beamformer for ultrasound imaging probes. - Peng Wang 013; Trond Ytterdal (ECCTD, 2015)

Surfing front-end architectures for ultrasound imaging systems. - Peng Wang 013; Trond Ytterdal; Thomas M. Halvorsrod (ECCTD, 2015)

Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study. - Hourieh Attarzadeh; Sung Kyu Lim; Trond Ytterdal (ISCAS, 2015)

A 4.5fJ/conversion-step 9-bit 35MS/s configurable-gain SAR ADC in a compact area. - Ye Xu; Pieter Harpe; Trond Ytterdal (ISCAS, 2015)

An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm. - Hourieh Attarzadeh; Snorre Aunet; Trond Ytterdal (NORCAS, 2015)

Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI. - Even Låte; Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (NORCAS, 2015)

In-Probe Ultrasound Beamformer Utilizing Switched-Current Analog RAM. - Surya Sharma; Trond Ytterdal (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A compiled 3.5fJ/conv.step 9b 20MS/s SAR ADC for wireless applications in 28nm FDSOI. - Carsten Wulff; Trond Ytterdal (ESSCIRC, 2016)

Steep slope transistors: Tunnel FETs and beyond. - Alan C. Seabaugh; Cristobal Alessandri; Mina Asghari Heidarlou; Hua-Min Li; Leitao Liu; Hao Lu 006; Sara Fathipour; Paolo Paletti; Pratyush Pandey; Trond Ytterdal (ESSDERC, 2016)

Neural network based on parametrically-pumped oscillators. - György Csaba; Trond Ytterdal; Wolfgang Porod (ICECS, 2016)

Noise transfer functions and loop filters especially suited for noise-shaping SAR ADCs. - Harald Garvik; Carsten Wulff; Trond Ytterdal (ISCAS, 2016)

28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block. - Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (MIXDES, 2016)

Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing. - Ali Asghar Vatanjou; Even Låte; Trond Ytterdal; Snorre Aunet (NORCAS, 2016)

Low noise, -50 dB second harmonic distortion single-ended to differential switched-capacitive variable gain amplifier for ultrasound imaging. - Peng Wang 013; Trond Ytterdal (IET Circuits Devices Syst., 2016)

Design and Analysis of a Stochastic Flash Analog-to-Digital Converter in 3D IC technology for integration with ultrasound transducer array. - Hourieh Attarzadeh; Sung Kyu Lim; Trond Ytterdal (Microelectron. J., 2016)

Low-power low-area beamformer design using switched-current ARAM using external capacitors. - Surya Sharma; Trond Ytterdal (Microelectron. J., 2016)

A 54-µW Inverter-Based Low-Noise Single-Ended to Differential VGA for Second Harmonic Ultrasound Probes in 65-nm CMOS. - Peng Wang 013; Trond Ytterdal (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimation. - Harald Garvik; Carsten Wulff; Trond Ytterdal (CICC, 2017)

A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers. - Carsten Wulff; Trond Ytterdal (IEEE J. Solid State Circuits, 2017)

Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. - Even Låte; Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (Microprocess. Microsystems, 2017)

A Low-Power High-Dynamic-Range Receiver System for In-Probe 3-D Ultrasonic Imaging. - Hourieh Attarzadeh; Ye Xu; Trond Ytterdal (IEEE Trans. Biomed. Circuits Syst., 2017)

A 1 MHz BW 34.2 fJ/step Continuous Time Delta Sigma Modulator With an Integrated Mixer for Cardiac Ultrasound. - Rune Kaald; Trym Eggen; Trond Ytterdal (IEEE Trans. Biomed. Circuits Syst., 2017)

Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NORCAS, 2018)

A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology. - Even Låte; Trond Ytterdal; Snorre Aunet (Integr., 2018)

Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing. - Ali Asghar Vatanjou; Even Låte; Trond Ytterdal; Snorre Aunet (Microprocess. Microsystems, 2018)

A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip CDAC Calibration. - Harald Garvik; Carsten Wulff; Trond Ytterdal (A-SSCC, 2019)

A High-Voltage Cascode-Connected Three-Level Pulse-Generator for Bio-Medical Ultrasound Applications. - Aslak Lykre Holen; Trond Ytterdal (ISCAS, 2019)

Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NORCAS, 2019)

Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NORCAS, 2019)

Modified Current-reuse OTA to Achieve High CMRR by utilizing Cross-coupled Load. - Erwin H. T. Shad; Marta Molinas; Trond Ytterdal (PRIME, 2019)

An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI. - Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Very Low SEF Neural Amplifier by Utilizing a High Swing Current-Reuse Amplifier. - Kebria Naderi; Erwin H. T. Shad; Marta Molinas; Ali Heidari; Trond Ytterdal (DCIS, 2020)

A Low-power and Low-noise Multi-purpose Chopper Amplifier with High CMRR and PSRR. - Erwin H. T. Shad; Marta Molinas; Trond Ytterdal (EMBC, 2020)

Emerging Josephson Junction/Graphene Device Technologies towards THz Signal Generation. - Zachary Cochran; Trond Ytterdal; Akul Madan; Maher E. Rizkalla (ISCAS, 2020)

A Low Power FinFET Charge Pump for Energy Harvesting Applications. - Kyle Whittaker; Maher E. Rizkalla; Trond Ytterdal (MWSCAS, 2020)

A Power Efficient, High Gain and High Input Impedance Capacitively-coupled Neural Amplifier. - Erwin H. T. Shad; Tania Moeinfard; Marta Molinas; Trond Ytterdal (NorCAS, 2020)

Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NorCAS, 2020)

Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NorCAS, 2020)

Plasmonic FET Terahertz Spectrometer. - Xueqing Liu 003; Trond Ytterdal; Michael S. Shur (IEEE Access, 2020)

An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V. - Even Låte; Trond Ytterdal; Snorre Aunet (IEEE Trans. Circuits Syst., 2020)

Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping. - Even Låte; Trond Ytterdal; Snorre Aunet (IEEE Trans. Very Large Scale Integr. Syst., 2020)

GNRFET-Based DC-DC Converters for Low Power Data Management in ULSI System, a Feasibility Study. - George Mekhael; Nathaniel Morgan; Mounica Patnala; Trond Ytterdal; Maher E. Rizkalla (ISCAS, 2021)

Implementation of High Speed and Low Power Carry Select Adder with BEC. - Nikhil Advaith Gudala; Trond Ytterdal; John J. Lee 001; Maher E. Rizkalla (MWSCAS, 2021)

Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NorCAS, 2021)

High-level Comparison of Control-Bounded A/D Converters and Continuous- Time Sigma-Delta Modulators. - Fredrik Feyling; Hampus Malmberg; Carsten Wulff; Hans-Andrea Loeliger; Trond Ytterdal (NorCAS, 2022)

A 160-GHz Power Amplifier with 32-dB Gain and 9.8% Peak PAE in 28-nm FD-SOI. - Shankkar Balasubramanian; Carsten Wulff; Trond Ytterdal (ISCAS, 2023)

Towards No Penalty Control Hazard Handling. - Linknath Surya Balasubramanian; Maher E. Rizkalla; Jaehwan Lee 002; Trond Ytterdal; Mukesh Kumar (MWSCAS, 2023)

SRAM Vmin Scaling via Negative Wordline. - Anoop Gopinath; Trond Ytterdal; Avinash Yadav; John J. Lee 001; Maher E. Rizkalla; Mukesh Kumar (MWSCAS, 2023)

Interfacing GaN HEMTs with Josephson Junctions: A Novel Approach to High-Frequency Electronics. - Elijah Racz; Arthur Thomas; Maher E. Rizkalla; Trond Ytterdal; John J. Lee 001 (MWSCAS, 2024)

Design and Analysis of the Leapfrog Control-Bounded A/D Converter. - Fredrik Feyling; Hampus Malmberg; Carsten Wulff; Hans-Andrea Loeliger; Trond Ytterdal (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Optimizing Energy Efficiency in Subthreshold RISC-V Cores. - Asbjørn Djupdal; Magnus Själander; Magnus Jahre; Snorre Aunet; Trond Ytterdal (CoRR, 2025)

Design of Area Efficient In-Memory Adder and Sum-Comparator with a Variable Reference Voltage Mechanism. - Linknath Surya Balasubramanian; Elijah Racz; Anoop Gopinath; Maher E. Rizkalla; John J. Lee 001; Trond Ytterdal; Mukesh Kumar (Circuits Syst. Signal Process., 2025)