ZipStream: Improving dependability in dynamic partial reconfiguration. - Stefano Di Carlo; Giulio Gambardella; Trong Huynh Bao; Paolo Prinetto; Daniele Rolfo; Pascal Trotta (IDT, 2013)

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. - Trong Huynh Bao; Dmitry Yakimets; Julien Ryckaert; Ivan Ciofi; Rogier Baert; Anabela Veloso; Jürgen Bömmels; Nadine Collaert; Philippe Roussel; S. Demuynck; Praveen Raghavan; Abdelkarim Mercha; et al. (ESSDERC, 2014)

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (ICICDT, 2015)

SRAM designs for 5nm node and beyond: Opportunities and challenges. - Trong Huynh Bao; Sushil Sakhare; Julien Ryckaert; Alessio Spessot; Diederik Verkest; Anda Mocuta (ICICDT, 2017)

Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems. - Manu Komalan; Sushil Sakhare; Trong Huynh Bao; Siddharth Rao; Woojin Kim; Christian Tenllado; José Ignacio Gómez; Gouri Sankar Kar; Arnaud Furnémont; Francky Catthoor (ISCAS, 2017)

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. - Trong Huynh Bao; Julien Ryckaert; Zsolt Tokei; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. - Trong Huynh Bao; Anabela Veloso; Sushil Sakhare; Philippe Matagne; Julien Ryckaert; Manu Perumkunnil; Davide Crotti; Farrukh Yasin; Alessio Spessot; Arnaud Furnémont; Gouri Sankar Kar; Anda Mocuta (DAC, 2019)