Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese. - Trong-Thuc Hoang; Hong-Kiet Su; Hieu-Binh Nguyen; Duc-Hung Le; Huu-Thuan Huynh; Trong-Tu Bui; Cong-Kha Pham (IEICE Electron. Express, 2015)

Low-resource low-latency hybrid adaptive CORDIC with floating-point precision. - Hong-Thu Nguyen; Xuan-Thuan Nguyen; Trong-Thuc Hoang; Duc-Hung Le; Cong-Kha Pham (IEICE Electron. Express, 2015)

A hybrid adaptive CORDIC in 65nm SOTB CMOS process. - Trong-Thuc Hoang; Duc-Hung Le; Hong-Thu Nguyen; Xuan-Thuan Nguyen; Cong-Kha Pham (ISCAS, 2016)

An efficient FPGA-based database processor for fast database analytics. - Xuan-Thuan Nguyen; Hong-Thu Nguyen; Trong-Thuc Hoang; Katsumi Inoue; Osamu Shimojo; Toshio Murayama; Kenji Tominaga; Cong-Kha Pham (ISCAS, 2016)

FPGA-based frequent items counting using matrix of equality comparators. - Trong-Thuc Hoang; Xuan-Thuan Nguyen; Hong-Thu Nguyen; Nhu-Quynh Truong; Duc-Hung Le; Katsumi Inoue; Cong-Kha Pham (MWSCAS, 2017)

High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC. - Trong-Thuc Hoang; Cong-Kha Pham; Duc-Hung Le (ISCAS, 2018)

A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS. - Xuan-Thuan Nguyen; Trong-Thuc Hoang; Hong-Thu Nguyen; Katsumi Inoue; Cong-Kha Pham (ISCAS, 2018)

VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations. - Trong-Thuc Hoang; Duc-Hung Le; Cong-Kha Pham (MCSoC, 2018)

VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study. - Katsumi Inoue; Trong-Thuc Hoang; Xuan-Thuan Nguyen; Hong-Thu Nguyen; Cong-Kha Pham (PRIME, 2018)

An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation. - Xuan-Thuan Nguyen; Trong-Thuc Hoang; Hong-Thu Nguyen; Katsumi Inoue; Cong-Kha Pham (IEEE Access, 2018)

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC. - Trong-Thuc Hoang; Duc-Hung Le; Cong-Kha Pham (IEICE Electron. Express, 2018)

Frequent items counter based on binary decoders. - Katsumi Inoue; Trong-Thuc Hoang; Cong-Kha Pham (IEICE Electron. Express, 2018)

A CORDIC-based QR decomposition for MIMO signal detector. - Hong-Thu Nguyen; Xuan-Thuan Nguyen; Trong-Thuc Hoang; Cong-Kha Pham (IEICE Electron. Express, 2018)

A 0.75-V 32-MHz 181-µW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC. - Ngoc-Tu Bui; Trong-Thuc Hoang; Duc-Hung Le; Cong-Kha Pham (ICIT, 2019)

Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter. - Takahiro Hosaka; Trong-Thuc Hoang; Van-Phuc Hoang; Duc-Hung Le; Katsumi Inoue; Cong-Kha Pham (ISCAS, 2019)

A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS. - Xuan-Thuan Nguyen; Trong-Thuc Hoang; Katsumi Inoue; Ngoc-Tu Bui; Van-Phuc Hoang; Cong-Kha Pham (ISCAS, 2019)

A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC. - Duc-Hung Le; Trong-Thuc Hoang; Cong-Kha Pham (IEICE Electron. Express, 2019)

A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB. - Xuan-Thuan Nguyen; Trong-Thuc Hoang; Hong-Thu Nguyen; Katsumi Inoue; Cong-Kha Pham (Microprocess. Microsystems, 2019)

Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias. - Trong-Thuc Hoang; Xuan-Thuan Nguyen; Duc-Hung Le; Cong-Kha Pham (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA. - Xuan-Thuan Nguyen; Trong-Thuc Hoang; Hong-Thu Nguyen; Katsumi Inoue; Cong-Kha Pham (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors. - Trong-Thuc Hoang; Ckristian Duran; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (ISCAS, 2020)

Quick Boot of Trusted Execution Environment With Hardware Accelerators. - Trong-Thuc Hoang; Ckristian Duran; Duc-Thinh Nguyen-Hoang; Duc-Hung Le; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2020)

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB). - Trong-Thuc Hoang; Ckristian Duran; Khai-Duy Nguyen; Tuan-Kiet Dang; Quynh Nguyen Quang Nhu; Phuc Hong Than; Xuan-Tu Tran; Duc-Hung Le; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEICE Electron. Express, 2020)

A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS. - Xuan-Thuan Nguyen; Trong-Thuc Hoang; Hong-Thu Nguyen; Katsumi Inoue; Cong-Kha Pham (Microprocess. Microsystems, 2020)

System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture. - Trong-Thuc Hoang; Ckristian Duran; Ronaldo Serrano; Marco Sarmiento; Khai-Duy Nguyen; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (HCS, 2021)

A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip. - Khai-Duy Nguyen; Tuan-Kiet Dang; Trong-Thuc Hoang; Quynh Nguyen Quang Nhu; Cong-Kha Pham (HCS, 2021)

ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3. - Ronaldo Serrano; Ckristian Duran; Trong-Thuc Hoang; Marco Sarmiento; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (ISOCC, 2021)

A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. - Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Khai-Duy Nguyen; Trong-Thuc Hoang; Koichiro Ishibashi; Cong-Kha Pham (ISOCC, 2021)

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks. - Ba-Anh Dao; Trong-Thuc Hoang; Anh-Tien Le; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2021)

Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure. - Ba-Anh Dao; Trong-Thuc Hoang; Anh-Tien Le; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2021)

A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor. - Anh-Tien Le; Trong-Thuc Hoang; Ba-Anh Dao; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2021)

A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse. - Ronaldo Serrano; Ckristian Duran; Trong-Thuc Hoang; Marco Sarmiento; Khai-Duy Nguyen; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2021)

A proposal for enhancing training speed in deep learning models based on memory activity survey. - Tuan-Kiet Dang; Binh Kieu-Do-Nguyen; Trong-Thuc Hoang; Khai-Duy Nguyen; Xuan-Tu Tran; Cong-Kha Pham (IEICE Electron. Express, 2021)

A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction. - Khai-Duy Nguyen; Tuan-Kiet Dang; Trong-Thuc Hoang; Quynh Nguyen Quang Nhu; Xuan-Tu Tran; Cong-Kha Pham (IEICE Electron. Express, 2021)

A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. - Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Trong-Thuc Hoang; Ronaldo Serrano; Van-Phuc Hoang; Xuan-Tu Tran; Koichiro Ishibashi; Cong-Kha Pham (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A System-on-Chip for IoT Applications with 16-bit Tiny Processor. - Tuan-Kiet Dang; Khai-Duy Nguyen; Quynh Nguyen Quang Nhu; Trong-Thuc Hoang; Cong-Kha Pham (ICICDT, 2022)

High-speed FPGA-based Design and Implementation of Text Search Processor. - Binh Kieu-Do-Nguyen; Tuan-Kiet Dang; Trong-Thuc Hoang; Katsumi Inoue; Toshinori Usugi; Masanori Odaka; Shuichi Kameyama; Cong-Kha Pham (ICICDT, 2022)

Spectre attack detection with Neutral Network on RISC-V processor. - Anh-Tien Le; Trong-Thuc Hoang; Ba-Anh Dao; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (ISCAS, 2022)

A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators. - Tuan-Kiet Dang; Ronaldo Serrano; Trong-Thuc Hoang; Cong-Kha Pham (ISOCC, 2022)

A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore. - Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Trong-Thuc Hoang; Cong-Kha Pham (ISOCC, 2022)

High-performance Multi-function HMAC-SHA2 FPGA Implementation. - Binh Kieu-Do-Nguyen; Trong-Thuc Hoang; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (NEWCAS, 2022)

Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling. - Trong-Thuc Hoang; Ckristian Duran; Ronaldo Serrano; Marco Sarmiento; Khai-Duy Nguyen; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2022)

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Trong-Thuc Hoang; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2022)

Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA. - Binh Kieu-Do-Nguyen; Cuong Pham-Quoc; Ngoc-Thinh Tran; Cong-Kha Pham; Trong-Thuc Hoang (Cryptogr., 2022)

ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Cong-Kha Pham; Trong-Thuc Hoang (Cryptogr., 2022)

A Unified PUF and Crypto Core Exploiting the Metastability in Latches. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Tuan-Kiet Dang; Trong-Thuc Hoang; Cong-Kha Pham (Future Internet, 2022)

Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications. - Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Ronaldo Serrano; Trong-Thuc Hoang; Koichiro Ishibashi; Cong-Kha Pham (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks. - Thai-Ha Tran; Anh-Tien Le; Trong-Thuc Hoang; Van-Phuc Hoang; Cong-Kha Pham (ACM Great Lakes Symposium on VLSI, 2023)

In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology. - Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Tuan-Kiet Dang; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2023)

Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks. - Van-Phuc Hoang; Ngoc-Tuan Do; Trong-Thuc Hoang; Cong-Kha Pham (MCSoC, 2023)

FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V. - Nguyen The Binh; Binh Kieu-Do-Nguyen; Trong-Thuc Hoang; Cong-Kha Pham; Cuong Pham-Quoc (RIVF, 2023)

Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor. - Binh Kieu-Do-Nguyen; Cuong Pham-Quoc; Ngoc-Thinh Tran; Cong-Kha Pham; Trong-Thuc Hoang (IEEE Access, 2023)

A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment. - Anh-Tien Le; Trong-Thuc Hoang; Ba-Anh Dao; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (Comput. Electr. Eng., 2023)

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA. - Khai-Minh Ma; Duc-Hung Le; Cong-Kha Pham; Trong-Thuc Hoang (Future Internet, 2023)

A Survey of Post-Quantum Cryptography: Start of a New Race. - Duc-Thuan Dam; Thai-Ha Tran; Van-Phuc Hoang; Cong-Kha Pham; Trong-Thuc Hoang (Cryptogr., 2023)

A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography. - Trong-Hung Nguyen; Cong-Kha Pham; Trong-Thuc Hoang (Cryptogr., 2023)

Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC. - Thai-Ha Tran; Ba-Anh Dao; Trong-Thuc Hoang; Van-Phuc Hoang; Cong-Kha Pham (IEEE Trans. Computers, 2023)

A True Random Number Generator on FPGA with Jitter-Sampling by Ring Generator. - Tuan-Kiet Dang; Trong-Thuc Hoang; Cong-Kha Pham (AsianHOST, 2024)

A Trusted Execution Environment RISC-V System on Chip. - Binh Kieu-Do-Nguyen; Khai-Duy Nguyen; Tuan-Kiet Dang; Cong-Kha Pham; Trong-Thuc Hoang (HCS, 2024)

RISC-V-Based System-on-Chips for IoT Applications. - Khai-Duy Nguyen; Tuan-Kiet Dang; Binh Kieu-Do-Nguyen; Cong-Kha Pham; Trong-Thuc Hoang (HCS, 2024)

Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding. - Nhu-Hoang Nguyen; Tan-Phat Dang; Thanh-Dat Bui; Trong-Thuc Hoang; Cong-Kha Pham; Huu-Thuan Huynh (ICCSA (Workshops 1), 2024)

A Strong 4 × 4 S-Box Using an Enhanced Tent Map. - Phuc-Phan Duong; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2024)

Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems. - Trong-Hung Nguyen; Nguyen The Binh; Huynh Phuc Nghi; Cong-Kha Pham; Trong-Thuc Hoang (ISCAS, 2024)

A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Khai-Duy Nguyen; Tetsuya Iizuka; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2024)

An Efficient Hiding Countermeasure with Xilinx MMCM Primitive in Spread Mode. - Thai-Ha Tran; Van-Phuc Hoang; Duc-Hung Le; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2024)

A Resource-Efficient Multi-core Multi-thread RISC-V-based System-on-Chip. - Binh Kieu-Do-Nguyen; Khai-Duy Nguyen; Nguyen The Binh; Tuan-Kiet Dang; Duc-Hung Le; Cuong Pham-Quoc; Ngoc-Thinh Tran; Cong-Kha Pham; Trong-Thuc Hoang (ISOCC, 2024)

An Efficient Method for Accelerating Kyber and Dilithium Post-Quantum Cryptography. - Duc-Thuan Dam; Trong-Hung Nguyen; Thai-Ha Tran; Binh Kieu-Do-Nguyen; Trong-Thuc Hoang; Cong-Kha Pham (PST, 2024)

Hardware Implementation of a Hybrid Dynamic Gold Code-Based Countermeasure Against Side-Channel Attacks. - Thai-Ha Tran; Duc-Thuan Dam; Binh Kieu-Do-Nguyen; Van-Phuc Hoang; Trong-Thuc Hoang; Cong-Kha Pham (PST, 2024)

High-Efficiency Multi-Standard Polynomial Multiplication Accelerator on RISC-V SoC for Post-Quantum Cryptography. - Duc-Thuan Dam; Trong-Hung Nguyen; Thai-Ha Tran; Duc-Hung Le; Trong-Thuc Hoang; Cong-Kha Pham (IEEE Access, 2024)

Construction of Robust Lightweight S-Boxes Using Enhanced Logistic and Enhanced Sine Maps. - Phuc-Phan Duong; Hieu Minh Nguyen 001; Ba-Anh Dao; Binh Kieu-Do-Nguyen; Thai-Ha Tran; Trong-Thuc Hoang; Cong-Kha Pham (IEEE Access, 2024)

Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System. - Binh Kieu-Do-Nguyen; Khai-Duy Nguyen; Nguyen The Binh; Khai-Minh Ma; Tri Duc Ta; Duc-Hung Le; Cong-Kha Pham; Trong-Thuc Hoang (IEEE Access, 2024)

High-Speed NTT Accelerator for CRYSTAL-Kyber and CRYSTAL-Dilithium. - Trong-Hung Nguyen; Binh Kieu-Do-Nguyen; Cong-Kha Pham; Trong-Thuc Hoang (IEEE Access, 2024)

A Novel ECG Signal Quality Index Method Based on Skewness-MODWT Analysis. - Ta Viet Tai; Ma Pham Nhut Tan; Duong Hoang Tien; Nguyen Viet Ha 002; Trong-Thuc Hoang; Cong-Kha Pham; Tran Thi Thao Nguyen (IEEE Access, 2024)

A multimode SHA-3 accelerator based on RISC-V system. - Huu-Thuan Huynh; Tan-Phat Dang; Tuan-Kiet Tran; Trong-Thuc Hoang; Cong-Kha Pham (IEICE Electron. Express, 2024)

Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm. - Thai-Ha Tran; Duc-Thuan Dam; Ba-Anh Dao; Van-Phuc Hoang; Cong-Kha Pham; Trong-Thuc Hoang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications. - Tuan-Kiet Dang; Khai-Duy Nguyen; Binh Kieu-Do-Nguyen; Trong-Thuc Hoang; Cong-Kha Pham (Future Internet, 2024)

Compact and Low-Latency FPGA-Based Number Theoretic Transform Architecture for CRYSTALS Kyber Postquantum Cryptography Scheme. - Binh Kieu-Do-Nguyen; Nguyen The Binh; Cuong Pham-Quoc; Huynh Phuc Nghi; Ngoc-Thinh Tran; Trong-Thuc Hoang; Cong-Kha Pham (Inf., 2024)

Accumulator-Based 16-Bit Processor for Wireless Sensor Nodes. - Tuan-Kiet Dang; Khai-Duy Nguyen; Cong-Kha Pham; Trong-Thuc Hoang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC. - Thai-Ha Tran; Ba-Anh Dao; Duc-Hung Le; Van-Phuc Hoang; Trong-Thuc Hoang; Cong-Kha Pham (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Pedestrian Avoidance Simulation by Deep Reinforcement Learning Using Webots. - Chalumpol Trararak; Trong-Thuc Hoang; Cong-Kha Pham (ICAIIC, 2025)

Dual-Mode PUF and TRNG Design with Ring Generator on 180nm CMOS. - Tuan-Kiet Dang; Khai-Duy Nguyen; Trong-Thuc Hoang; Cong-Kha Pham (ICICDT, 2025)

Compact FALCON FFT/NTT Accelerator for Post-Quantum Cryptography. - Duc-Thuan Dam; Thai-Ha Tran; Trong-Hung Nguyen; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2025)

A Low-Latency Polynomial Arithmetic Unit for ML-KEM and ML-DSA Standards. - Trong-Hung Nguyen; Duc-Thuan Dam; Phuc-Phan Duong; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2025)

Live Demonstration: ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications. - Khai-Duy Nguyen; Tuan-Kiet Dang; Binh Kieu-Do-Nguyen; Cong-Kha Pham; Trong-Thuc Hoang (ISCAS, 2025)

Enhanced Tower Field Mask Scheme with Affine Transformation-based Dynamic S-box. - Thai-Ha Tran; Duc-Thuan Dam; Van-Phuc Hoang; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2025)

An Area-Time Efficient Hardware Architecture for ML-KEM Post-Quantum Cryptography Standard. - Trong-Hung Nguyen; Tuan-Kiet Dang; Duc-Thuan Dam; Khai-Duy Nguyen; Phuc-Phan Duong; Cong-Kha Pham; Trong-Thuc Hoang (IEEE Access, 2025)

Compact 8-Bit S-Boxes Based on Multiplication in a Galois Field GF(24). - Phuc-Phan Duong; Tuan-Kiet Dang; Trong-Thuc Hoang; Cong-Kha Pham (Cryptogr., 2025)

ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications. - Khai-Duy Nguyen; Tuan-Kiet Dang; Binh Kieu-Do-Nguyen; Duc-Hung Le; Cong-Kha Pham; Trong-Thuc Hoang (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Efficient Hardware Implementation of the Lightweight CRYSTALS-Kyber. - Trong-Hung Nguyen; Duc-Thuan Dam; Phuc-Phan Duong; Binh Kieu-Do-Nguyen; Cong-Kha Pham; Trong-Thuc Hoang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)