Developing integrated antenna subsystems for laptop computers. - Duixian Liu; Brian P. Gaucher; Ephraim B. Flint; Thomas W. Studwell; Hideyuki Usui; Troy J. Beukema (IBM J. Res. Dev., 2003)

A direct-conversion receiver integrated circuit for WCDMA mobile systems. - Scott K. Reynolds; Brian A. Floyd; Troy J. Beukema; Thomas Zwick; Ullrich R. Pfeiffer; Herschel A. Ainspan (IBM J. Res. Dev., 2003)

A direct-conversion receiver IC for WCDMA mobile systems. - Scott K. Reynolds; Brian A. Floyd; Troy J. Beukema; Thomas Zwick; Ullrich R. Pfeiffer; Herschel A. Ainspan (IEEE J. Solid State Circuits, 2003)

Progress toward a low-cost millimeter-wave silicon radio. - Scott K. Reynolds; Brian A. Floyd; Ullrich R. Pfeiffer; Troy J. Beukema; Thomas Zwick; Janus Grzyb; Duixian Liu; Brian P. Gaucher (CICC, 2005)

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization. - Troy J. Beukema; Michael Sorna; Karl Selander; Steven Zier; Brian L. Ji; Phil Murfet; James Mason; Woogeun Rhee; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes (IEEE J. Solid State Circuits, 2005)

SiGe bipolar transceiver circuits operating at 60 GHz. - Brian A. Floyd; Scott K. Reynolds; Ullrich R. Pfeiffer; Thomas Zwick; Troy J. Beukema; Brian P. Gaucher (IEEE J. Solid State Circuits, 2005)

Design and Compliance Testing of a SiGe WCDMA Receiver IC With Integrated Analog Baseband. - Scott K. Reynolds; Brian A. Floyd; Troy J. Beukema; Thomas Zwick; Ullrich R. Pfeiffer (Proc. IEEE, 2005)

Wideband Channel Sounder With Measurements and Model for the 60 GHz Indoor Radio Channel. - Thomas Zwick; Troy J. Beukema; Haewoon Nam (IEEE Trans. Veh. Technol., 2005)

A silicon 60GHz receiver and transmitter chipset for broadband communications. - Brian A. Floyd; Scott K. Reynolds; Ullrich R. Pfeiffer; Troy J. Beukema; Janus Grzyb; Chuck Haymes (ISSCC, 2006)

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. - Mounir Meghelli; Sergey V. Rylov; John F. Bulzacchelli; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; L. Shan; et al. (ISSCC, 2006)

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. - John F. Bulzacchelli; Mounir Meghelli; Sergey V. Rylov; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; Lei Shan; et al. (IEEE J. Solid State Circuits, 2006)

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications. - Scott K. Reynolds; Brian A. Floyd; Ullrich R. Pfeiffer; Troy J. Beukema; Janusz Grzyb; Chuck Haymes; Brian P. Gaucher; Mehmet Soyuer (IEEE J. Solid State Circuits, 2006)

2-Gbps Uncompressed HDTV Transmission over 60-GHz SiGe Radio Link. - Yasunao Katayama; Chuck Haymes; Daiju Nakano; Troy J. Beukema; Brian A. Floyd; Scott K. Reynolds; Ullrich R. Pfeiffer; Brian P. Gaucher; Kai Schleupen (CCNC, 2007)

Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers. - Alberto Valdes-Garcia; Scott K. Reynolds; Troy J. Beukema (CICC, 2007)

Multi-Gbps wireless systems over 60-GHz SiGe radio link with BW-efficient noncoherent detections. - Yasunao Katayama; Daiju Nakano; Alberto Valdes-Garcia; Troy J. Beukema; Scott K. Reynolds (ICME, 2008)

Design considerations for high-data-rate chip interconnect systems. - Troy J. Beukema (IEEE Commun. Mag., 2010)

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. - Jean-Olivier Plouchart; Mihai A. T. Sanduleanu; Zeynep Toprak Deniz; Troy J. Beukema; Scott K. Reynolds; Benjamin D. Parker; Michael P. Beakes; José A. Tierno; Daniel J. Friedman (CICC, 2012)

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. - John F. Bulzacchelli; Troy J. Beukema; Daniel W. Storaska; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Christian Menolfi; David Hanson; Juergen Hertle; Thomas Morf; et al. (ISSCC, 2012)

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. - John F. Bulzacchelli; Christian Menolfi; Troy J. Beukema; Daniel W. Storaska; Juergen Hertle; David Hanson; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Thomas Morf; et al. (IEEE J. Solid State Circuits, 2012)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. - Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Daniel Dreps; Troy J. Beukema; Andrea Prati 002; Daniele Gardellini; Marcel A. Kossel; Peter Buchmann; Matthias Braendli; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2012)

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os. - Thomas Toifl; Peter Buchmann; Troy J. Beukema; Michael P. Beakes; Matthias Braendli; Pier Andrea Francese; Christian Menolfi; Marcel A. Kossel; Lukas Kull; Thomas Morf (ESSCIRC, 2014)

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. - Sergey V. Rylov; Troy J. Beukema; Zeynep Toprak Deniz; Thomas Toifl; Yong Liu 023; Ankur Agrawal; Peter Buchmann; Alexander V. Rylyakov; Michael P. Beakes; Benjamin D. Parker; Mounir Meghelli (ISSCC, 2016)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)