Floating Point Processor for the VAX 8600. - Tryggve Fossum; William J. Grundmann; Virginia Blaha (COMPCON, 1985)

The Microarchitecture of the VAX 8600. - Fernando C. Colón Osorio; Tryggve Fossum; William Hilliard; William Brucket; Paul Guglielmo; John Bloem (COMPCON, 1985)

Designing a VAX for high performance. - Tryggve Fossum; David B. Fite (Compcon, 1990)

Cache Scrubbing in Microprocessors: Myth or Necessity? - Shubhendu S. Mukherjee; Joel S. Emer; Tryggve Fossum; Steven K. Reinhardt (PRDC, 2004)

On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing. - Tryggve Fossum (Hot Interconnects, 2007)

Multi Core Design for Chip Level Multiprocessing. - Tryggve Fossum (LASER Summer School, 2008)

DEC Alpha. - Joel S. Emer; Tryggve Fossum (Encyclopedia of Parallel Computing, 2011)

Using in-flight chains to build a scalable cache coherence protocol. - Samantika Subramaniam; Simon C. Steely Jr.; William Hasenplaugh; Aamer Jaleel; Carl J. Beckmann; Tryggve Fossum; Joel S. Emer (ACM Trans. Archit. Code Optim., 2013)

Simulating stencil-based application on future Xeon Phi processor. - Chitra Natarajan; Carl J. Beckmann; Anthony Nguyen; Mauricio Araya-Polo; Tryggve Fossum; Detlef Hohl (PMBS@SC, 2015)