Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). - Yu-Chung Lin; Su-Feng Tseng; Tsai-Ming Hsieh (FPGA, 2000)

Minimum crosstalk channel routing with dogleg. - Kuo-Chih Hsu; Yu-Chung Lin; Po-Xun Chiu; Tsai-Ming Hsieh (ISCAS, 2000)

Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. - Po-Xun Chiu; Yu-Chung Lin; Yi-Ling Hsieh; Tsai-Ming Hsieh (ISCAS (5), 2001)

An efficient hierarchical approach for general floorplan area minimization. - Chih-Hung Lee; Wen-Yu Fu; Chung-Chiao Chang; Tsai-Ming Hsieh (APCCAS (2), 2002)

A New Formulation for SOC Floorplan Area Minimization Problem. - Chih-Hung Lee; Yu-Chung Lin; Wen-Yu Fu; Chung-Chiao Chang; Tsai-Ming Hsieh (DATE, 2002)

Sequence-pair based placement with boundary constraints. - Chih-Hung Lee; Yi-Lin Hsieh; Hui-Chun Lee; Tsai-Ming Hsieh (ISCAS (1), 2002)

Structural Decomposition with Functional Considerations for Low Power. - Chih-Hung Lee; Yu-Chung Lin; Hsin-Hsiung Huang; Tsai-Ming Hsieh (ISQED, 2002)

A New Effective Congestion Model in Floorplan Design. - Yi-Lin Hsieh; Tsai-Ming Hsieh (DATE, 2004)

Floorplanning with clock tree estimation. - Chih-Hung Lee; Chin-Hung Su; Shih-Hsu Huang; Chih-Yuan Lin; Tsai-Ming Hsieh (ISCAS (6), 2005)

A new congestion and crosstalk aware router. - Chin-Hui Wang; Yung-Ching Chen; Tsai-Ming Hsieh; Chih-Hung Lee; Hsin-Hsiung Huang (ISCAS (6), 2005)

A congestion-driven buffer planner with space reservation. - Hsin-Hsiung Huang; Yung-Ching Chen; Tsai-Ming Hsieh (ISCAS, 2006)

Timing-driven X-architecture router among rectangular obstacles. - Hsin-Hsiung Huang; Shu-Ping Chang; Yu-Cheng Lin; Tsai-Ming Hsieh (ISCAS, 2008)

Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. - Hsin-Hsiung Huang; Hui-Yu Huang; Yu-Cheng Lin; Tsai-Ming Hsieh (ISCAS, 2008)

Technology remapping for engineering change with wirelength consideration. - Jui-Hung Hung; Yao-Kai Yeh; Yung-Sheng Tseng; Tsai-Ming Hsieh (ISCAS, 2010)

Optimal Supply Voltage Assignment under Timing, Power and Area Constraints. - Hsi-An Chien; Cheng-Chiang Lin; Hsin-Hsiung Huang; Tsai-Ming Hsieh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A new ECO technology for functional changes and removing timing violations. - Jui-Hung Hung; Yao-Kai Yeh; Yung-Sheng Tseng; Tsai-Ming Hsieh (ISQED, 2011)

Wire Planning for Electromigration and Interference Avoidance in Analog Circuits. - Hsin-Hsiung Huang; Jui-Hung Hung; Cheng-Chiang Lin; Tsai-Ming Hsieh (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Image Retrieval based on color and texture features. - Chin-Hung Su; Mohd Helmy Abd Wahab; Tsai-Ming Hsieh (FSKD, 2012)

A logic difference generator with spare cells consideration for ECO synthesis. - Jui-Hung Hung; Yu-Cheng Lin; Wei-Kai Cheng; Tsai-Ming Hsieh (ISQED, 2015)

Unified approach for simultaneous functional and timing ECO. - Jui-Hung Hung; Yu-Cheng Lin; Wei-Kai Cheng; Tsai-Ming Hsieh (IET Circuits Devices Syst., 2016)