PLAYGROUND: Minimization of PLAs with Mixed Ground True Outputs. - Chin-Long Wey; Tsin-Yuan Chang (DAC, 1988)

Design of fault diagnosable and repairable PLA's. - Tsin-Yuan Chang; Chin-Long Wey (IEEE J. Solid State Circuits, 1989)

Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. - Chin-Long Wey; Jyhyeung Ding; Tsin-Yuan Chang (DAC, 1990)

An efficient output phase assignment for PLA minimization. - Chin-Long Wey; Tsin-Yuan Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Design of fault-diagnosable and repairable folded PLAs for yield enhancement. - Chin-Long Wey; Tsin-Yuan Chang; Jyhyeuan Ding (IEEE J. Solid State Circuits, 1991)

A design for concurrent error detections in FPLAs. - Tsin-Yuan Chang; Jean-Bean Hsu; Cheng-Chi Wang; Yu-Shen Lin (Great Lakes Symposium on VLSI, 1992)

Two schemes for detecting CMOS analog faults. - Tsin-Yuan Chang; Cheng-Chi Wang; Jain-Bean Hsu (IEEE J. Solid State Circuits, 1992)

A Programmable BIST Core for Embedded DRAM. - Chih-Tsun Huang; Jing-Reng Huang; Chi-Feng Wu; Cheng-Wen Wu; Tsin-Yuan Chang (IEEE Des. Test Comput., 1999)

SoC Testing and P1500 Standard. - Tsin-Yuan Chang; Yervant Zorian (Asian Test Symposium, 2000)

A realistic fault model for flash memories. - Yea-Ling Horng; Jing-Reng Huang; Tsin-Yuan Chang (Asian Test Symposium, 2000)

An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters. - Jeng-Horng Tsai; Ming-Jun Hsiao; Tsin-Yuan Chang (Asian Test Symposium, 2001)

A low-cost CMOS time interval measurement core. - Ming-Jun Hsiao; Jing-Reng Huang; Shao-Shen Yang; Tsin-Yuan Chang (ISCAS (4), 2001)

A built-in timing parametric measurement unit. - Ming-Jun Hsiao; Jing-Reng Huang; Shao-Shen Yang; Tsin-Yuan Chang (ITC, 2001)

An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters. - Sheng-Hung Hsieh; Ming-Jun Hsiao; Tsin-Yuan Chang (Asian Test Symposium, 2002)

An Access Timing Measurement Unit of Embedded Memory. - Shu-Rong Lee; Ming-Jun Hsiao; Tsin-Yuan Chang (Asian Test Symposium, 2002)

A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers. - Shao-Sheng Yang; Pao-Lin Guo; Tsin-Yuan Chang; Jin-Hua Hong (ISCAS (5), 2003)

Timing measurement unit with multi-stage TVC for embedded memories. - Kae-Jiun Mo; Shao-Sheng Yang; Tsin-Yuan Chang (ASP-DAC, 2004)

A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier. - Yi-Ming Sheng; Ming-Jun Hsiao; Tsin-Yuan Chang (Asian Test Symposium, 2004)

A Built-In Parametric Timing Measurement Unit. - Ming-Jun Hsiao; Jing-Reng Huang; Tsin-Yuan Chang (IEEE Des. Test Comput., 2004)

On-chip accumulated jitter measurement for phase-locked loops. - Chih-Feng Li; Shao-Sheng Yang; Tsin-Yuan Chang (ASP-DAC, 2005)

A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency Range. - Chung-Yi Li; Chia-yuan Chou; Tsin-Yuan Chang (ATS, 2006)

A chaos-based pseudo random number generator using timing-based reseeding method. - Chung-Yi Li; Jiung-Sheng Chen; Tsin-Yuan Chang (ISCAS, 2006)

A current mode adaptive on-time control scheme for fast transient DC-DC converters. - Hung-Chih Lin; Bou-Ching Fung; Tsin-Yuan Chang (ISCAS, 2008)

An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES. - Chung-Yi Li; Chih-Feng Chien; Jin-Hua Hong; Tsin-Yuan Chang (ISVLSI, 2008)

An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement. - Hung-Chih Lin; Hsiang-Han Wu; Tsin-Yuan Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

IEEE Standard 1500 Compatible Delay Test Framework. - Po-Lin Chen; Jhih-Wei Lin; Tsin-Yuan Chang (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500. - Po-Lin Chen; Yu-Chieh Huang; Tsin-Yuan Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A 2.4-GS/s FFT Processor for OFDM-Based WPAN Applications. - Song-Nien Tang; Jui-Wei Tsai; Tsin-Yuan Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias. - Yuan-Ho Chen; Chung-Yi Li; Tsin-Yuan Chang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications. - Chung-Yi Li; Yuan-Ho Chen; Tsin-Yuan Chang; Jyun-Neng Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree. - Yuan-Ho Chen; Tsin-Yuan Chang; Chung-Yi Li (IEEE Trans. Very Large Scale Integr. Syst., 2011)

An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems. - Song-Nien Tang; Chi-Hsiang Liao; Tsin-Yuan Chang (IEEE J. Solid State Circuits, 2012)

A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers. - Yuan-Ho Chen; Tsin-Yuan Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy. - Yuan-Ho Chen; Tsin-Yuan Chang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG. - Chung-Yi Li; Yuan-Ho Chen; Tsin-Yuan Chang; Lih-Yuan Deng; Kiwing To (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A low-power Spread Spectrum Clock Generator with an embeddable half-integer division ratio interpolator. - Hsi-En Liu; Shih-Che Hung; Chih-Wen Lu; Tsin-Yuan Chang (ISCAS, 2014)

High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic. - Yuan-Ho Chen; Jyun-Neng Chen; Tsin-Yuan Chang; Chih-Wen Lu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy. - Yuan-Ho Chen; Ruei-Yuan Jou; Tsin-Yuan Chang; Chih-Wen Lu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display. - Chih-Wen Lu; Pei-Yi Lai Lee; You-Gang Chang; Xing-Wei Huang; Jhih-Siou Cheng; Po-Yu Tseng; Chih-Hsien Chou; Poki Chen; Tsin-Yuan Chang; Jenny Yi-Chun Liu (IEEE J. Solid State Circuits, 2019)