Partition methodology for the final adder in a tree-structure parallel multiplier generator. - Tso-Bing Juang; Jeng-Hsiun Jan; Ming-Yu Tsai; Shen-Fu Hsiao (APCCAS (1), 2002)

A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations. - Shen-Fu Hsiao; Yu Hen Hu; Tso-Bing Juang (IEEE Signal Process. Lett., 2004)

Para-CORDIC: parallel CORDIC rotation algorithm. - Tso-Bing Juang; Shen-Fu Hsiao; Ming-Yu Tsai (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition. - Tso-Bing Juang; Shen-Fu Hsiao; Ming-Yu Tsai; Jenq-Shiun Jan (IEICE Trans. Inf. Syst., 2005)

Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design. - Shen-Fu Hsiao; Yu Hen Hu; Tso-Bing Juang; Cheng-Han Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Low-error carry-free fixed-width multipliers with low-cost compensation circuits. - Tso-Bing Juang; Shen-Fu Hsiao (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations. - Tso-Bing Juang (APCCAS, 2006)

A novel VLSI iterative divider architecture for fast quotient generation. - Tso-Bing Juang; Sheng-Hung Chen; Shin-Mao Li (ISCAS, 2008)

Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations. - Tso-Bing Juang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications. - Tso-Bing Juang; Sheng-Hung Chen; Huang-Jia Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Corrections to "VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection" [Sep 08 897-901]. - Tso-Bing Juang; Ming-Yu Tsai; Chin-Chieh Chiu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

50 Years of CORDIC: Algorithms, Architectures, and Applications. - Pramod Kumar Meher; Javier Valls; Tso-Bing Juang; K. Sridharan 001; Koushik Maharatna (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Area-efficient parallel-prefix Ling adders. - Tso-Bing Juang; Pramod Kumar Meher; Chung-Chun Kuan (APCCAS, 2010)

Improved Area-Efficient Weighted Modulo 2n + 1 Adder Design With Simple Correction Schemes. - Tso-Bing Juang; Chin-Chieh Chiu; Ming-Yu Tsai (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Area-efficient 3-input decimal adders using simplified carry and sum vectors. - Tso-Bing Juang; Hsin-Hao Peng; Chao-Tsung Kuo (VLSI-SoC, 2011)

Multifunction RNS modulo (2n±1) multipliers based on modified booth encoding. - Tso-Bing Juang; Jian-Hao Huang (APCCAS, 2012)

A lower error antilogarithmic converter using novel four-region piecewise-linear approximation. - Chao-Tsung Kuo; Tso-Bing Juang (APCCAS, 2012)

Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders. - Tso-Bing Juang; Hsin-Hao Peng; Han-Lung Kuo (ISOCC, 2012)

Multifunction RNS Modulo 2n ± 1 Multipliers. - Tso-Bing Juang; Chao-Tsung Kuo; Go-Long Wu; Jian-Hao Huang (J. Circuits Syst. Comput., 2012)

Fast binary to BCD converters for decimal communications using new recoding circuits. - Tso-Bing Juang; Yu-Ming Chiu (ISIC, 2014)

Low-cost concurrent error detection schemes for logarithmic converters. - Tso-Bing Juang; Ying-Ren Lee; Chin-Chieh Chiu (ISOCC, 2016)

Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications. - Tso-Bing Juang; Ying-Ren Lee (ISVLSI, 2016)

Low-area implementations of concurrent error detection logarithmic processors. - Tso-Bing Juang; Ying-Ren Lee (ISOCC, 2017)

Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems. - Tso-Bing Juang; Cong-Yi Lin; Guan-Zhong Lin (ISOCC, 2018)

Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems. - Tso-Bing Juang; Cong-Yi Lin; Guan-Zhong Lin (ISOCC, 2019)

Lower-Error and Area-Efficient Complex Divider Design using Logarithmic Number Systems (LNS). - Tso-Bing Juang; Chun-Chi Fan; Guan-Zhong Lin (ISOCC, 2023)

Design of Automatic Generators for Fibonacci Q- matrix based Encryption/Decryption Circuits. - Tso-Bing Juang; Huang-Sen Chiu (ISOCC, 2024)