Test Vector Minimization During Logic Synthesis. - Tsu-Wei Ku; Wei-Kong Chia (ICCAD, 1990)

Minimal overhead modification of iterative logic arrays for C-testability. - Tsu-Wei Ku; Mani Soma (ITC, 1990)

A Sequential Test Generator with Explicit Elimination of Easy-to-Test Faults. - Tsu-Wei Ku; Wei-Kong Chia (ITC, 1991)