An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. - Jin-Fu Li 001; Tsu-Wei Tseng; Chin-Long Wey (DATE, 2005)

A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. - Tsu-Wei Tseng; Jin-Fu Li 001; Da-Ming Chang (DATE, 2006)

A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs. - Tsu-Wei Tseng; Jin-Fu Li 001; Chih-Chiang Hsu; Alex Pao; Kevin Chiu; Eliot Chen (ITC, 2006)

A Built-In Self-Repair Scheme for Multiport RAMs. - Tsu-Wei Tseng; Chun-Hsien Wu; Yu-Jen Huang; Jin-Fu Li 001; Alex Pao; Kevin Chiu; Eliot Chen (VTS, 2007)

ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. - Chao-Da Huang; Jin-Fu Li 001; Tsu-Wei Tseng (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs. - Tsu-Wei Tseng; Jin-Fu Li 001 (ITC, 2008)

Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. - Tsu-Wei Tseng; Chih-Sheng Hou; Jin-Fu Li 001 (VTS, 2010)

A Built-in Method to Repair SoC RAMs in Parallel. - Tsu-Wei Tseng; Jin-Fu Li 001; Chih-Sheng Hou (IEEE Des. Test Comput., 2010)

DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs. - Tsu-Wei Tseng; Yu-Jen Huang; Jin-Fu Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults. - Jin-Fu Li 001; Tsu-Wei Tseng; Chih-Sheng Hou (IEEE Trans. Very Large Scale Integr. Syst., 2010)

ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs. - Tsu-Wei Tseng; Jin-Fu Li 001; Chih-Chiang Hsu (IEEE Trans. Very Large Scale Integr. Syst., 2010)

SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories. - Tsu-Wei Tseng; Jin-Fu Li 001 (J. Inf. Sci. Eng., 2011)

Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. - Chih-Sheng Hou; Jin-Fu Li 001; Tsu-Wei Tseng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy. - Tsu-Wei Tseng; Jin-Fu Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

3-D centric technology and realization with TSV. - Chang-Tzu Lin; Chia-Hsin Lee; Tsu-Wei Tseng; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2012)

Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs. - Ting-Ju Chen; Jin-Fu Li 001; Tsu-Wei Tseng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Enabling inter-die co-optimization in 3-D IC with TSVs. - Chang-Tzu Lin; Tsu-Wei Tseng; Yung-Fa Chou; Chia-Hsin Lee; Ding-Ming Kwai (VLSI-DAT, 2013)

A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. - Tsu-Wei Tseng; Chang-Tzu Lin; Chia-Hsin Lee; Yung-Fa Chou; Ding-Ming Kwai (VLSI-DAT, 2014)