A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs. - Hiroki Fujisawa; Tsugio Takahashi; Masayuki Nakamura; Kazuhiko Kajigaya (IEEE J. Solid State Circuits, 2001)

A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. - Tsugio Takahashi; Tomonori Sekiguchi; Riichiro Takemura; Seiji Narui; Hiroki Fujisawa; Shinichi Miyatake; Makoto Morino; Koji Arai; Satoru Yamada; Shoji Shukuri; Masayuki Nakamura; Yoshitaka Tadaki; et al. (IEEE J. Solid State Circuits, 2001)

A low-impedance open-bitline array for multigigabit DRAM. - Tomonori Sekiguchi; Kiyoo Itoh 001; Tsugio Takahashi; Masahiro Sugaya; Hiroki Fujisawa; Masayuki Nakamura; Kazuhiko Kajigaya; Katsutaka Kimura (IEEE J. Solid State Circuits, 2002)

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. - Tatsuya Matano; Yasuhiro Takai; Tsugio Takahashi; Yuusuke Sakito; Isamu Fujii; Yoshihiro Takaishi; Hiroki Fujisawa; Shuichi Kubouchi; Seiji Narui; Koji Arai; Makoto Morino; Masayuki Nakamura; et al. (IEEE J. Solid State Circuits, 2003)

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems. - Yasushi Amamiya; Shunichi Kaeriyama; Hidemi Noguchi; Zin Yamazaki; Tomoyuki Yamase; Ken'ichi Hosoya; Minoru Okamoto; Shiro Tomari; Hiroshi Yamaguchi; Hiroaki Shoda; Hironobu Ikeda; Shinji Tanaka; et al. (ISSCC, 2009)

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems. - Shunichi Kaeriyama; Yasushi Amamiya; Hidemi Noguchi; Zin Yamazaki; Tomoyuki Yamase; Ken'ichi Hosoya; Minoru Okamoto; Shiro Tomari; Hiroshi Yamaguchi; Hiroaki Shoda; Hironobu Ikeda; Shinji Tanaka; et al. (IEEE J. Solid State Circuits, 2009)