A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module. - Tsugumichi Shibata; Shunji Kimura; Hideaki Kimura 002; Yuhki Imai; Yohtaro Umeda; Yukio Akazawa (IEEE J. Solid State Circuits, 1994)

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator. - Hideyuki Nosaka; Kiyoshi Ishii; Takatomo Enoki; Tsugumichi Shibata (IEEE J. Solid State Circuits, 2003)

High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]. - Kiyoshi Ishii; Hideyuki Nosaka; Minoru Ida; Kenji Kurishima; Michihiro Hirata; Takatorno Enoki; Tsugumichi Shibata (ESSCIRC, 2004)

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. - Hideyuki Nosaka; Eiichi Sano; Kiyoshi Ishii; Minoru Ida; Kenji Kurishima; Shoji Yamahata; Tsugumichi Shibata; Hiroyuki Fukuyama; Mikio Yoneyama; Takatomo Enoki; Masahiro Muraguchi (IEEE J. Solid State Circuits, 2004)

A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation. - Hideyuki Nosaka; Makoto Nakamura; Kimikazu Sano; Minoru Ida; Kenji Kurishima; Tsugumichi Shibata; Masami Tokumitsu; Masahiro Muraguchi (IEICE Trans. Electron., 2005)

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. - Kiyoshi Ishii; Hideyuki Nosaka; Kimikazu Sano; Koichi Murata; Minoru Ida; Kenji Kurishima; Michihiro Hirata; Tsugumichi Shibata; Takatomo Enoki (IEEE J. Solid State Circuits, 2005)

A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON. - Shoko Ohteru; Tomoaki Kawamura; Hiroki Suto; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (A-SSCC, 2011)

Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction. - Hiroyuki Uzawa; Kazuhiko Terada; Namiko Ikeda; Akihiko Miyazaki; Masami Urano; Tsugumichi Shibata (GLOBECOM, 2011)

10G/1G dual-rate EPON OLT LSI with dual encryption modes alternated using DBA-information-based algorithm control. - Sadayuki Yasuda; Takahiro Hatano; Hiroki Suto; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (ISOCC, 2011)

An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System. - Hiroaki Katsurai; Hideki Kamitsuna; Hiroshi Koizumi; Jun Terada; Yusuke Ohtomo; Tsugumichi Shibata (IEICE Trans. Electron., 2011)

Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs. - Naoki Miura; Akihiko Miyazaki; Junichi Kato; Nobuyuki Tanaka; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (ISCAS, 2012)

A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI. - Sadayuki Yasuda; Shoko Ohteru; Yasuyuki Itoh; Koji Yamazaki; Yusuke Sekihara; Takashi Aoki; Masami Urano; Tsugumichi Shibata (IEICE Electron. Express, 2013)

Foreword. - Tsugumichi Shibata (IEICE Trans. Electron., 2014)

An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU. - Ryota Takasu; Yoichi Tomioka; Yutaro Ishigaki; Ning Li; Tsugumichi Shibata; Mamoru Nakanishi; Hitoshi Kitazawa (IEICE Trans. Electron., 2014)

An FPGA implementation of 3D numerical simulations on a 2D SIMD array processor. - Yutaro Ishigaki; Yoichi Tomioka; Tsugumichi Shibata; Hitoshi Kitazawa (ISCAS, 2015)

Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip. - Naoki Miura; Akihiko Miyazaki; Junichi Kato; Nobuyuki Tanaka; Satoshi Shigematsu; Masami Urano; Mamoru Nakanishi; Tsugumichi Shibata (IEICE Trans. Electron., 2015)

A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer. - Chunhui Pan; Hao San; Tsugumichi Shibata (ISPACS, 2016)

A 2nd-order ΔΣAD modulator using ring amplifier and SAR quantizer with simplified operation mode. - Chunhui Pan; Hao San; Tsugumichi Shibata (MIXDES, 2017)

A 720µW 77.93dB SNDR ΔΣ AD Modulator Using Dynamic Analog Components With Simplified Operation Phase. - Chunhui Pan; Hao San; Tsugumichi Shibata (ISPACS, 2018)

Characterization of Multi-Layer Ceramic Chip Capacitors up to mm-Wave Frequencies for High-Speed Digital Signal Coupling. - Tsugumichi Shibata; Yoshito Kato (IEICE Trans. Electron., 2020)

An Indoor Positioning with a Neural Network Model of TensorFlow for Machine Learning. - Bojun Zheng; Takefumi Masuda; Tsugumichi Shibata (ISPACS, 2021)