A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation. - Tsuguo Kobayashi; Kazutaka Nogami; Tsukasa Shirotori; Yukihiro Fujimoto; Yoshitaka Biwaki; Haruo Nohara; Makiji Kobayashi; Kiyoshi Kobayashi; Kazuhiro Sawada (IEEE J. Solid State Circuits, 1991)

A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. - Tsuguo Kobayashi; Kazutaka Nogami; Tsukasa Shirotori; Yukihiro Fujimoto (IEEE J. Solid State Circuits, 1993)

A 110-MHz/1-Mb synchronous TagRAM. - Yasuo Unekawa; Tsuguo Kobayashi; Tsukasa Shirotori; Yukihiro Fujimoto; Takayoshi Shimazawa; Kazutaka Nogami; Takehiko Nakao; Kazukiro Sawada; Masataka Matsui; Takayasu Sakurai; Man Kit Tang; William A. Huffman (IEEE J. Solid State Circuits, 1994)