A New Array Architecture for Parallel Testing in VLSI Memories. - Yoshio Matsuda; Kazutami Arimoto; Masaki Tsukude; Tsukasa Oishi; Kazuyasu Fujishima (ITC, 1989)

A 34-ns 16-Mb DRAM with controllable voltage down-converter. - Hideto Hidaka; Kazutami Arimoto; Kazutoshi Hirayama; Masanori Hayashikoshi; Mikio Asakura; Masaki Tsukude; Tsukasa Oishi; Shinji Kawai; Katsuhiro Suma; Yasuhiro Konishi; Koji Tanaka; Wataru Wakamiya; et al. (IEEE J. Solid State Circuits, 1992)

An 8kB EEPROM-Emulation DataFLASH Module for Automotive MCU. - Shinji Kawai; Akira Hosogane; Shigehiro Kuge; Toshihiro Abe; Kohei Hashimoto; Tsukasa Oishi; Naoki Tsuji; Kiyohiko Sakakibara; Kenji Noguchi (ISSCC, 2008)

0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers. - Yasunobu Nakase; Shinichi Hirose; Toru Goda; Kehui Hu; Hiroshi Onoda; Yasuhiro Ido; Hiroyuki Kondo; Wei Kong; Wei Zhang; Tsukasa Oishi; Shintaro Mori; Toru Shimizu (A-SSCC, 2011)

A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration. - Yasunobu Nakase; Shinichi Hirose; Hiroshi Onoda; Yasuhiro Ido; Yoshiaki Shimizu; Tsukasa Oishi; Toshio Kumamoto; Toru Shimizu (CICC, 2012)

On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes. - Yasunobu Nakase; Yasuhiro Ido; Tsukasa Oishi; Toru Shimizu (IEICE Trans. Electron., 2013)

0.5 V Start-Up 87% Efficiency 0.75 mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration. - Yasunobu Nakase; Shinichi Hirose; Hiroshi Onoda; Yasuhiro Ido; Yoshiaki Shimizu; Tsukasa Oishi; Toshio Kumamoto; Toru Shimizu (IEEE J. Solid State Circuits, 2013)

A low power NoC router using the marching memory through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (COOL Chips, 2014)

Design of a low power NoC router using Marching Memory Through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (NOCS, 2014)