A speed-enhanced DRAM array architecture with embedded ECC. - Kazutami Arimoto; Yoshio Matsuda; Kiyohiro Furutani; Masaki Tsukude; Tsukasa Ooishi; Koichiro Mashiko; Kuzuyasu Fujishima (IEEE J. Solid State Circuits, 1990)

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. - Tsukasa Ooishi; Mikio Asakura; Shigeki Tomishima; Hideto Hidaka; Kazutami Arimoto; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1994)

An experimental 256-Mb DRAM with boosted sense-ground scheme. - Mikio Asakura; Tsukasa Ooishi; Masaki Tsukude; Shigeki Tomishima; Takahisa Eimori; Hideto Hidaka; Yoshikazu Ohno; Kazutani Arimoto; Kazuyasu Fujishima; Tadashi Nishimura; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1994)

An automatic temperature compensation of internal sense ground for subquarter micron DRAM's. - Tsukasa Ooishi; Yuichiro Komiya; Kei Hamade; Mho Asakura; Kenichi Yasuda; Kiyohiro Furutani; Hideto Hidaka; Hiroshi Miyamoto; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1995)

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. - Tsukasa Ooishi; Yuichiro Komiya; Kei Hamade; Mikio Asakura; Kenichi Yasuda; Kiyohiro Furutani; Tetsuo Kato; Hideto Hidaka; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1996)

A 99-mm2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system. - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Yusuke Kanehira; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; et al. (CICC, 2001)

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. - Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Masatoshi Ishikawa; Toshihiro Inokuchi; Hiroshi Kato; Hiroaki Tanizaki; Wataru Abe; Akinori Shibayama; Yoshifumi Fukushima; Mitsutaka Niiro; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2001)

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. - Hirohito Kikukawa; Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Shouji Sakamoto; Masatoshi Ishikawa; Wataru Abe; Hiroaki Tanizaki; Hiroshi Kato; Toshitaka Uchikoba; Toshihiro Inokuchi; Manabu Senoh; et al. (IEEE J. Solid State Circuits, 2002)

A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system. - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; Shin-ichi Hattori; et al. (IEEE J. Solid State Circuits, 2002)