Resistance ratio read (R3) architecture for a burst operated 1.5V MRAM macro. - Tsuneo Inaba; Kenji Tsuchida; Tadahiko Sugibayashi; Shuichi Tahara; Hiroaki Yoda (CICC, 2003)

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. - Yoshihisa Iwata; Kenji Tsuchida; Tsuneo Inaba; Yui Shimizu; R. Takizawa; Yoshihiro Ueda; Tadahiko Sugibayashi; Yoshiaki Asao; Takeshi Kajiyama; Keiji Hosotani; Sumio Ikegawa; Tadashi Kai; et al. (ISSCC, 2006)

A 64Mb MRAM with clamped-reference and adequate-reference schemes. - Kenji Tsuchida; Tsuneo Inaba; Katsuyuki Fujita; Yoshihiro Ueda; Takafumi Shimizu; Yoshiaki Asao; Takeshi Kajiyama; Masayoshi Iwayama; Kuniaki Sugiura; Sumio Ikegawa; Tatsuya Kishi; Tadashi Kai; et al. (ISSCC, 2010)

23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. - Kwangmyoung Rho; Kenji Tsuchida; Dongkeun Kim; Yutaka Shirai; Jihyae Bae; Tsuneo Inaba; Hiromi Noro; Hyunin Moon; Sungwoong Chung; Kazumasa Sunouchi; Jinwon Park; Kiseon Park; et al. (ISSCC, 2017)