A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions. - Takashi Nakayama; Hisao Harigai; Shingo Kojima; Hiroaki Kaneko; Hatsuhide Igarashi; Tsuneo Toba; Yutaka Yamagami; Yoichi Yano (IEEE J. Solid State Circuits, 1989)