Analysis and Definition of Overall Timing Accuracy in VLSI Test System. - Shigeru Sugamori; Kenji Yoshida; Hiromi Maruyama; Shinpei Kamata; Tsuneta Sudo (ITC, 1981)

Hierarchical top-down layout design method for VLSI chip. - Tohru Adachi; Hitoshi Kitazawa; Mitsuyoshi Nagatani; Tsuneta Sudo (DAC, 1982)

A large scale cellular array processor: AAP-1. - Toshio Kondo; Tayoshi Nakashima; Toshio Tsuchiya; Yoshi Sugiyama; Tsuneta Sudo (ACM Conference on Computer Science, 1985)

Semiconductor Device Simulation at NTT. - Kiyoyuki Yokoyama; Masaaki Tomizawa; Akira Yoshii; Tsuneta Sudo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

Software Environment for 500 MHz VLSI Test System "ULTIMATE". - Tohru Adachi; M. Tanno; Tsuneta Sudo (ITC, 1988)

Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE". - Yoshimitsu Sakagawa; Yusio Akazawa; Naoaki Narumi; Akira Yoshii; Tsuneta Sudo (ITC, 1988)

Key Technologies for 500 MHz VLSI Test System "ULTIMATE". - Teruo Tamama; Naoaki Narumi; Tai-ichi Otsuji; Masao Suzuki; Tsuneta Sudo (ITC, 1988)

Design automation systems in Japan. - Tsuneta Sudo (IEEE Des. Test, 1988)