A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique. - Tsung-Chih Hung; Tai-Haur Kuo (A-SSCC, 2016)

A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth. - Tsung-Chih Hung; Tai-Haur Kuo (CICC, 2019)

A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with Averaging Correlated Level Shifting Technique. - Jia-Ching Wang; Tsung-Chih Hung; Tai-Haur Kuo (VLSI-DAT, 2019)

A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch. - Tsung-Chih Hung; Tai-Haur Kuo (IEEE J. Solid State Circuits, 2019)

A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4, 000 Conversions/Channel. - Tsung-Chih Hung; Fan-Wei Liao; Tai-Haur Kuo (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Feasibility Study of Introducing Daily Rental Suites Business Model into Long-Term Care Institutions. - Kuei-Yuan Wang; Ying-Li Lin; Chien-Kuo Han; Tsung-Chih Hung (IMIS, 2020)

16.4 A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme. - Tsung-Chih Hung; Jia-Ching Wang; Tai-Haur Kuo (ISSCC, 2020)

A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique. - Jia-Ching Wang; Tsung-Chih Hung; Tai-Haur Kuo (IEEE J. Solid State Circuits, 2020)

24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC. - Cheng-En Hsieh; Gabriele Manganaro; Sheng-Hui Liao; Jack Weng; Tsun-Yuan Fan; Alec Chin; Tsung-Chih Hung; Jonathan X. Wu; Chi-Lun Lo; Andy Pan; Ming-Hang Hsieh; Yun-Shiang Shu; et al. (ISSCC, 2025)