Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. - Kuen-Jong Lee; Jing-Jou Tang; Tsung-Chu Huang; Cheng-Liang Tsai (Asian Test Symposium, 1996)

Built-in current sensor designs based on the bulk-driven technique. - Tsung-Chu Huang; Min-Cheng Huang; Kuen-Jong Lee (Asian Test Symposium, 1997)

An Input Control Technique for Power Reduction in Scan Circuits During Test Application. - Tsung-Chu Huang; Kuen-Jong Lee (Asian Test Symposium, 1999)

BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. - Kuen-Jong Lee; Jing-Jou Tang; Tsung-Chu Huang (ACM Trans. Design Autom. Electr. Syst., 1999)

Peak-power reduction for multiple-scan circuits during test application. - Kuen-Jong Lee; Tsung-Chu Huang; Jih-Jeen Chen (Asian Test Symposium, 2000)

A Low-Power LFSR Architecture. - Tsung-Chu Huang; Kuen-Jong Lee (Asian Test Symposium, 2001)

A token scan architecture for low power testing. - Tsung-Chu Huang; Kuen-Jong Lee (ITC, 2001)

Reduction of power consumption in scan-based circuits during testapplication by an input control technique. - Tsung-Chu Huang; Kuen-Jong Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. - Kuen-Jong Lee; Tsung-Chu Huang (J. Electron. Test., 2002)

Congruence Synchronous Mirror Delay. - Tsung-Chu Huang; Gau-Bin Chang; Ling Li (ISCAS, 2007)

A Low-Power Dependable Berger Code for Fully Asymmetric Communication. - Tsung-Chu Huang (IEEE Commun. Lett., 2008)

Multi-valued equal-weight codes for self-checking and matching. - Tsung-Chu Huang (IEEE Commun. Lett., 2009)

HYPERA: High-Yield Performance-Efficient Redundancy Analysis. - Tsung-Chu Huang; Kuei-Yeh Lu; Yen-Chieh Huang (Asian Test Symposium, 2010)

High-yield performance-efficient redundancy analysis for 2D memory. - Tsung-Chu Huang (Sci. China Inf. Sci., 2011)

Cluster Error Correction for Real-Time Channels by Unbound Rotation of Two-Dimensional Parity-Check Codes. - Tsung-Chu Huang (IEEE Commun. Lett., 2015)

Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. - Tsung-Chu Huang; Jeffae Schroff (ATS, 2018)

Self-Checking Residue Number System for Low-Power Reliable Neural Network. - Tsung-Chu Huang (ATS, 2019)

Low-Cost and Fast Design of Precise Activation Functions in Neural Network. - Tsung-Chu Huang; Chun-Hao Chiang; Mo-Han Lin (ICCE-TW, 2019)

Residue Number System Design Automation for Neural Network Acceleration. - Liang-Yu Lin; Jerrae Schroff; Tsu-Ping Lin; Tsung-Chu Huang (ICCE-TW, 2020)

Approximate Computing for Batch Learning in Neural Network. - Liang-Yu Lin; Jerrae Schroff; Chia-Cheng Liang; Tsung-Chu Huang (ICCE-TW, 2020)

Range-Lookup Approximate Computing Acceleration for Any Activation Functions in Low-Power Neural Network. - Wen-Chang Yang; Shu-Yun Lin; Tsung-Chu Huang (ICCE-TW, 2020)

TCBNN: Error-Correctable Ternary-Coded Binarized Neural Network. - Cheng-Di Tsai; Ting-Yu Chen; Hsiao-Wen Fu; Tsung-Chu Huang (AICAS, 2021)

Error Correctable Range-Addressable Lookup for Activation and Quantization in AI Automotive Electronics. - Ting-Yu Chen; Cheng-Di Tsai; Hsiao-Wen Fu; Yung-Chun Yang; Tsung-Chu Huang (ICCE-TW, 2021)

AN-Coded Redundant Residue Number System for Reliable Neural Networks. - Hsiao-Wen Fu; Ting-Yu Chen; Cheng-Di Tsai; Meng-Wei Shen; Tsung-Chu Huang (ICCE-TW, 2021)

SAFER & SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for Data Annotation and Early Warning in Online Aging Monitors of Automotive SoCs. - Cho-Sheng Lin; Jing Huang; Po-Sheng Chang; Chun-Yen Tsai; Tsung-Chu Huang (ICCE-TW, 2021)

TAIWAN Online: Test AI with AN Codes Online for Automotive Chips. - Cheng-Di Tsai; Hsiao-Wen Fu; Ting-Yu Chen; Tsung-Chu Huang (ITC-Asia, 2021)

AN-HRNS: AN-Coded Hierarchical Residue Number System for Reliable Neural Network Accelerators. - Wan Ju Huang; Hsiao-Wen Fu; Tsung-Chu Huang (ATS, 2022)

2DAN-BNN: Two-Dimensional AN-Code Decoders for Binarized Neural Networks. - Kuan-Yu Huang; Jettae Schroff; Cheng-Di Tsai; Tsung-Chu Huang (ICCE-TW, 2022)

SPINDLE: Self-Pretrainable In-situ Normalizer for Deep Learning Error Function. - Jyun-Xin Ke; Siang-En Ciou; Ting-Yu Chen; Tsung-Chu Huang (ICCE-TW, 2022)

TCB Convolution: Ternary-Coded Binarized Convolutions with Fixed-Point Filters. - Ting-Yu Chen; Zong-Yu Wang; Tsung-Chu Huang (ICCE-Taiwan, 2023)

Redundant Lagrange Interpolation for Fault-Tolerant Winograd Convolution. - Che Lin; Heng Hsu; Tsung-Chu Huang (ICCE-Taiwan, 2023)

Flosit: Float/Posit Coarchitecture Exploiting Value Location in Neural Network. - Yu-Liang Chen; Ren-Xiang Liu; Tsung-Chu Huang (ICCE-Taiwan, 2024)

SievingNet: Ternary-Coded Binary Based Approximate Sieving for Neural Network. - Chia-Yu Chou; Tzu-Yi Hung; Tsung-Chu Huang (ICCE-Taiwan, 2024)