CMOS front end components for micropower RF wireless systems. - Tsung-Hsien Lin 001; Henry Sanchez; Razieh Rofougaran; William J. Kaiser (ISLPED, 1998)

CMOS front-end LNA-mixer of micropower RF wireless systems. - Razieh Rofougaran; Tsung-Hsien Lin 001; William J. Kaiser (ISLPED, 1999)

A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop. - Tsung-Hsien Lin 001; William J. Kaiser (CICC, 2000)

A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard. - Arya Behzad; Zhong Ming Shi; Seema Butala Anand; Li Lin; Keith A. Carter; Michael S. Kappes; Tsung-Hsien Lin 001; Thinh Nguyen; Dan Yuan; Stephen Wu 003; Y. C. Wong; Victor Fong; et al. (IEEE J. Solid State Circuits, 2003)

Integrated low-power communication system design for wireless sensor networks. - Tsung-Hsien Lin 001; William J. Kaiser; Gregory J. Pottie (IEEE Commun. Mag., 2004)

Low-Power Radio Design for Wireless Smart Sensor Networks. - Wai-Chi Fang; Tsung-Hsien Lin 001 (IIH-MSP, 2006)

An energy-efficient 1.5-Mbps wireless FSK transmitter with A ∑Δ-modulated phase rotator. - Yao-Hong Liu; Tsung-Hsien Lin 001 (ESSCIRC, 2007)

A Single-Chip Bluetooth EDR Device in 0.13μm CMOS. - Bojko Marholev; Michael Pan; Ed Chien; L. Zhang; Rozi Roufoogaran; Steve Wu 001; Iqbal Bhatti; Tsung-Hsien Lin 001; Michael S. Kappes; Shahla Khorram; Seema Butala Anand; Alireza Zolfaghari; et al. (ISSCC, 2007)

An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL. - Tsung-Hsien Lin 001; Yu-Jen Lai (IEEE J. Solid State Circuits, 2007)

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS. - Tsung-Hsien Lin 001; Chin-Kung Wu; Ming-Chung Tsai (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 3.5-mW 15-Mbps O-QPSK transmitter for real-time wireless medical imaging applications. - Yao-Hong Liu; Tsung-Hsien Lin 001 (CICC, 2008)

A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit. - Ching-Lung Ti; Yao-Hong Liu; Tsung-Hsien Lin 001 (ISCAS, 2008)

A Wideband PLL-Based G/FSK Transmitter in 0.18 µm CMOS. - Yao-Hong Liu; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2009)

Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional- N PLLs. - Tsung-Hsien Lin 001; Ching-Lung Ti; Yao-Hong Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS. - Wei-Hao Chiu; Chien-Yuan Cheng; Tsung-Hsien Lin 001 (ISCAS, 2010)

Dual-mode Continuous-Time Quadrature Bandpass ΔΣ modulator with Pseudo-random Quadrature mismatch shaping algorithm for Low-IF receiver application. - Chen-Yen Ho; Yung-Yu Lin; Tsung-Hsien Lin 001 (ISCAS, 2010)

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops. - Wei-Hao Chiu; Yu-Hsiang Huang; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2010)

A Delta-Sigma Pulse-Width Digitization Technique for Super-Regenerative Receivers. - Yao-Hong Liu; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2010)

A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter. - Yu-Cheng Chang; Wei-Hao Chiu; Chen-Chien Lin; Tsung-Hsien Lin 001 (A-SSCC, 2011)

An energy-efficient super-regenerative ASK receiver with a ΔΣ-based pulse-width demodulator. - Po-Yun Hsiao; Yao-Hong Liu; Tsung-Hsien Lin 001 (A-SSCC, 2011)

A 15-mW 2.4-GHz IEEE 802.15.4 transmitter with a FIR-embedded phase modulator. - Yao-Hong Liu; Hao-Hung Lo; Li-Guang Chen; Tsung-Hsien Lin 001 (A-SSCC, 2011)

A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver. - Chen-Yen Ho; Wei-Shan Chan; Yung-Yu Lin; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2011)

A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation. - Chan-Hsiang Weng; Chen-Chien Lin; Yu-Cheng Chang; Tsung-Hsien Lin 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Synchronous 50% Duty-Cycle Clock Generator in 0.35- μ m CMOS. - Tsung-Hsien Lin 001; Chao-Ching Chi; Wei-Hao Chiu; Yu-Hsiang Huang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A sensor-merged oscillator-based readout circuit for pizeo-resistive sensing applications. - Yi-Lin Tsai; Po-Yun Hsiao; Li-Guang Chen; Che-Wei Huang; Hsiao-Ting Hsueh; Chih-Chan Tu; Chih-Ting Lin; Shey-Shi Lu; Tsung-Hsien Lin 001 (BioCAS, 2012)

An energy-efficient ultra-wideband transmitter with an FIR pulse-shaping filter. - Wei-Ning Liu; Tsung-Hsien Lin 001 (VLSI-DAT, 2012)

Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). - Shen-Iuan Liu; Tsung-Hsien Lin 001; Woogeun Rhee (IEEE J. Solid State Circuits, 2012)

A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer. - Chen-Chien Lin; Chan-Hsiang Weng; Tsung-Hsien Lin 001 (VLSI-DAT, 2013)

A CMOS Cantilever-Based Label-Free DNA SoC With Improved Sensitivity for Hepatitis B Virus Detection. - Yu-Jie Huang; Che-Wei Huang; Tsung-Hsien Lin 001; Chih-Ting Lin; Li-Guang Chen; Po-Yun Hsiao; Bi-Ru Wu; Hsiao-Ting Hsueh; Bing-Jye Kuo; Hann-Huei Tsai; Hsin-Hao Liao; Ying-Zong Juang; et al. (IEEE Trans. Biomed. Circuits Syst., 2013)

A 650-pJ/bit MedRadio Transmitter With an FIR-Embedded Phase Modulator for Medical Micro-Power Networks (MMNs). - Yao-Hong Liu; Li-Guang Chen; Chun-Yu Lin 002; Tsung-Hsien Lin 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

An area-efficient capacitively-coupled instrumentation amplifier with a duty-cycled Gm-C DC servo loop in 0.18-μm CMOS. - Chih-Chan Tu; Feng-Wen Lee; Tsung-Hsien Lin 001 (A-SSCC, 2014)

A 135-μW 0.46-mΩ/√Hz thoracic impedance variance monitor with square-wave current modulation. - Chih-Chan Tu; Feng-Wen Lee; Dong-Feng Yeih; Tsung-Hsien Lin 001 (A-SSCC, 2014)

A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C. - Chan-Hsiang Weng; Chun-Kuan Wu; Tsung-Hsien Lin 001 (A-SSCC, 2014)

An Energy-Efficient QPSK Demodulation Scheme with Injection-Locking Technique for Green Radio Communication. - Fu-Chien Huang; Bang-Cyuan Wang; Yi-Lin Tsai; Tsung-Hsien Lin 001 (iThings/GreenCom/CPSCom, 2014)

LMS-based digital background linearization technique for VCO-based delta-sigma ADC. - Fu-Chien Huang; Shou-Chen Hsu; Yi-Lin Tsai; Yung-Yu Lin; Tsung-Hsien Lin 001 (MWSCAS, 2014)

Analog front-end amplifier for ECG applications with feed-forward EOS cancellation. - Chih-Chan Tu; Tsung-Hsien Lin 001 (VLSI-DAT, 2014)

A 400MHz 10Mbps D-BPSK receiver with a reference-less dynamic phase-to-amplitude demodulation technique. - Yi-Lin Tsai; Jian-You Chen; Bang-Cyuan Wang; Tzu-Yu Yeh; Tsung-Hsien Lin 001 (VLSIC, 2014)

An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS. - Chan-Hsiang Weng; Tzu-An Wei; Erkan Alpman; Chang-Tsung Fu; Yi-Ting Tseng; Tsung-Hsien Lin 001 (VLSIC, 2014)

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator. - Chen-Chien Lin; Chan-Hsiang Weng; Tzu-An Wei; Yung-Yu Lin; Tsung-Hsien Lin 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS. - Chan-Hsiang Weng; Wei-Hsiang Huang; Erkan Alpman; Tsung-Hsien Lin 001 (A-SSCC, 2015)

EP2: Lost art? Analog tricks and techniques from the masters. - Tsung-Hsien Lin 001; Carlo Samori; Richard Schreier (ISSCC, 2015)

5.3 A 2-channel -83.2dB crosstalk 0.061mm2 CCIA with an orthogonal frequency chopping technique. - Yi-Lin Tsai; Feng-Wen Lee; Tzu-Ying Chen; Tsung-Hsien Lin 001 (ISSCC, 2015)

A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer. - Chan-Hsiang Weng; Tzu-An Wei; Tsung-Hsien Lin 001 (VLSI-DAT, 2015)

A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ°C2. - Chan-Hsiang Weng; Chun-Kuan Wu; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2015)

A 4-GHz ΔΣ fractional-N frequency synthesizer with 2-dimensional quantization noise pushing and fractional spur elimination techniques. - Chun-Yu Lin 002; Tsung-Hsien Lin 001 (A-SSCC, 2016)

An area-efficient wideband CMOS hall sensor system for camera autofocus systems. - Chih-Chan Tu; Kuan-Chung Chen; Tsung-Yu Wu; Tsung-Hsien Lin 001 (A-SSCC, 2016)

A 40-nV/VHz 0.0145-mm2 sensor readout circuit with chopped VCO-based CTDSM in 40-nm CMOS. - Chih-Chan Tu; Yu-Kai Wang; Tsung-Hsien Lin 001 (A-SSCC, 2016)

A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer. - Chan-Hsiang Weng; Tzu-An Wei; Erkan Alpman; Chang-Tsung Fu; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2016)

A 330-µW 400-MHz BPSK Transmitter in 0.18- µm CMOS for Biomedical Applications. - Yi-Lin Tsai; Chun-Yu Lin 002; Bang-Cyuan Wang; Tsung-Hsien Lin 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS. - Chun-Yu Lin 002; Tun-Ju Wang; Tsung-Hsien Lin 001 (A-SSCC, 2017)

An ultra-low power 169-nA 32.768-kHz fractional-N PLL. - Chun-Yu Lin 002; Tun-Ju Wang; Tzu-Hsuan Liu; Tsung-Hsien Lin 001 (A-SSCC, 2017)

An area-efficient capacitively-coupled sensor readout circuit with current-splitting OTA and FIR-DAC. - Chih-Chan Tu; Feng-Wen Lee; Han-Chun Chen; Yu-Kai Wang; Tsung-Hsien Lin 001 (A-SSCC, 2017)

A Low-Noise Area-Efficient Chopped VCO-Based CTDSM for Sensor Applications in 40-nm CMOS. - Chih-Chan Tu; Yu-Kai Wang; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2017)

A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer. - Chan-Hsiang Weng; Yung-Yu Lin; Tsung-Hsien Lin 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC). - Tsung-Hsien Lin 001; Chia-Hsiang Yang; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS. - Chun-Yu Lin 002; Yu-Ting Hung; Tsung-Hsien Lin 001 (A-SSCC, 2019)

An Area-Efficient VCO-Based Hall Sensor Readout System for Autofocus Applications. - Pei-Hsuan Huang; Chih-Chan Tu; Tsung-Hsien Lin 001 (ISCAS, 2019)

An Analog Front-End Circuit for CO2 Sensor Readout in 0.18-µm CMOS Process. - Deng-Kai Lin; Chih-Chan Tu; Shih-Kai Kuo; Tsung-Hsien Lin 001 (VLSI-DAT, 2019)

A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique. - Chun-Yu Lin 002; Tun-Ju Wang; Yu-Ting Hung; Tsung-Hsien Lin 001 (VLSI-DAT, 2020)

Design of a 0.6-V, 429-MHz FSK Transceiver Using Q-Enhanced and Direct Power Transfer Techniques in 90-nm CMOS. - Chun-Yuan Chiu; Zhen-Cheng Zhang; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2020)

A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration. - Chun-Yu Lin 002; Yu-Wei Huang; Tsung-Hsien Lin 001 (A-SSCC, 2021)

29.5 A 0.008mm2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration. - Chun-Yu Lin 002; Yu-Ting Hung; Tun-Ju Wang; Tsung-Hsien Lin 001 (ISSCC, 2021)

Intelligent Wireless EEG Measurement System With Electrical and Optogenetic Stimulation for Epileptic Seizure Detection and Suppression. - Wei-En Lee; Chieh Tsou; Zhan-Xian Liao; Po-Yen Lu; Tsung-Hsien Lin 001; Shuenn-Yuh Lee; Chou-Ching K. Lin; Gia-Shing Shieh (IEEE Access, 2021)

A Temperature-Compensated Crystal Oscillator With Piecewise Polynomial Varactor Compensation Achieving ±3.75-ppm Inaccuracy From -30°C to 90°C. - Chun-Yu Lin 002; Yu-Wei Huang; Tsung-Hsien Lin 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.6-V 12-bit Set-and-Down SAR ADC With a DAC-Based Bypass Window Switching Method. - Wei-En Lee; Tsung-Hsien Lin 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration. - Chun-Yu Lin 002; Wei-Han Chen; Yu-Ting Hung; Tun-Ju Wang; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2024)

A Time-Domain Current-Mode Buck Converter With a PI Compensator Incorporating an Infinite Phase Shift Delay Line. - Mao-Ling Chiu; I-Fang Lo; Tsung-Hsien Lin 001 (IEEE J. Solid State Circuits, 2025)