Real-Time DSP Implementation on Local Stereo Matching. - Nelson Yen-Chung Chang; Ting-Min Lin; Tsung-Hsien Tsai; Yu-Cheng Tseng; Tian-Sheuan Chang (ICME, 2007)

Case Based Models to Predict Final Sales: A Test of Railway Passenger Arrivals. - Tsung-Hsien Tsai (DMIN, 2008)

Data reuse analysis of local stereo matching. - Tsung-Hsien Tsai; Nelson Yen-Chung Chang; Tian-Sheuan Chang (ISCAS, 2008)

A temporal case retrieval model to predict railway passenger arrivals. - Tsung-Hsien Tsai (Expert Syst. Appl., 2009)

Neural network based temporal feature models for short-term railway passenger demand forecasting. - Tsung-Hsien Tsai; Chi-Kang Lee; Chien-Hung Wei (Expert Syst. Appl., 2009)

Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight. - Nelson Yen-Chung Chang; Tsung-Hsien Tsai; Po-Hsiung Hsu; Yi-Chun Chen; Tian-Sheuan Chang (IEEE Trans. Circuits Syst. Video Technol., 2010)

A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector. - Yao-Chia Liu; Wei-Zen Chen; Mao-Hsuan Chou; Tsung-Hsien Tsai; Yen-Wei Lee; Min-Shueh Yuan (CICC, 2013)

A new sky recognition with using location of sky subimage. - Yu-Kumg Chen; Tsung-Hsien Tsai (ICIA, 2013)

Sky recognitions for driving-view images. - Yu-Kumg Chen; Tsung-Hsien Tsai (ICVES, 2013)

Real-time vehicle color identification using symmetrical SURFs and chromatic strength. - Li-Chih Chen; Jun-Wei Hsieh; Hui-Fen Chiang; Tsung-Hsien Tsai (ISCAS, 2015)

14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S. - Tsung-Hsien Tsai; Min-Shueh Yuan; Chih-Hsien Chang; Chia-Chun Liao; Chao-Chieh Li; Robert Bogdan Staszewski (ISSCC, 2015)

Dynamic flow aggregation in SDNs for application-aware routing. - Tsung-Hsien Tsai; Kuochen Wang; Tzu-Yu Chao (CSNDSP, 2016)

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. - Chao-Chieh Li; Tsung-Hsien Tsai; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Kenny Hsieh; Mark Chen 001; Augusto Ronchini Ximenes; et al. (VLSI Circuits, 2016)

Comparison of Several Confidence Intervals for Median Residual Lifetime with Left-truncated and Right-censored Data. - Yunchan Chi; Tsung-Hsien Tsai; Yi-Hsuan Tu; Wen-Yan Tsai (Commun. Stat. Simul. Comput., 2016)

Air-writing recognition using reverse time ordered stroke context. - Tsung-Hsien Tsai; Jun-Wei Hsieh (ICIP, 2017)

A Cooperative Multihop Transmission Scheme for Two-Way Amplify-and-Forward Relay Networks. - Chin-Liang Wang; Ting-Nan Cho; Tsung-Hsien Tsai; Min-Chau Jan (IEEE Trans. Veh. Technol., 2017)

A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW. - Tsung-Hsien Tsai; Ruey-Bin Sheen; Chih-Hsien Chang; Robert Bogdan Staszewski (VLSI Circuits, 2018)

A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS. - Wei-Chih Chen; Chin-Hua Wen; Chin-Ming Fu; Tsung-Hsien Tsai; Yu-Chi Chen; Wen-Hung Huang; Chien-Chun Tsai; Alvin Leng Sun Loke; C. H. Kenny (VLSI Circuits, 2020)

Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. - Mao-Hsuan Chou; Ya-Tin Chang; Tsung-Hsien Tsai; Tsung-Che Lu; Chia-Chun Liao; Hung-Yi Kuo; Ruey-Bin Sheen; Chih-Hsien Chang; Kenny C.-H. Hsieh; Alvin Leng Sun Loke; Mark Chen 001 (VLSI Circuits, 2020)

Self-evolutionary sibling models to forecast railway arrivals using reservation data. - Tsung-Hsien Tsai (Eng. Appl. Artif. Intell., 2020)

Air-writing recognition using reverse time ordered stroke context. - Tsung-Hsien Tsai; Jun-Wei Hsieh; Chuan-Wang Chang; Chin-Rong Lay; Kuo-Chin Fan (J. Vis. Commun. Image Represent., 2021)

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS. - Chao-Chieh Li; Min-Shueh Yuan; Chia-Chun Liao; Chih-Hsien Chang; Yu-Tso Lin; Tsung-Hsien Tsai; Tien-Chien Huang; Hsien-Yuan Liao; Chung-Ting Lu; Hung-Yi Kuo; Augusto Ronchini Ximenes; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. - Tsung-Hsien Tsai; Ruey-Bin Sheen; Sheng-Yun Hsu; Ya-Tin Chang; Chih-Hsien Chang; Robert Bogdan Staszewski (ISSCC, 2022)

Discovering a trans-omics biomarker signature that predisposes high risk diabetic patients to diabetic kidney disease. - I-Wen Wu; Tsung-Hsien Tsai; Chi-Jen Lo; Yi-Ju Chou; Chi-Hsiao Yeh; Yun-Hsuan Chan; Jun-Hong Chen; Paul Wei-Che Hsu; Heng-Chih Pan; Heng-Jung Hsu; Chun-Yu Chen; Chin-Chan Lee; et al. (npj Digit. Medicine, 2022)

Agile combination of advanced booking models for short-term railway arrival forecasting. - Tsung-Hsien Tsai (Eng. Appl. Artif. Intell., 2025)