Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement. - Tong-Yu Hsieh; Chih-Hao Wang; Chun-Wei Kuo; Shu-Yu Huang; Tsung-Liang Chih (J. Electron. Test., 2015)

A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies. - Tong-Yu Hsieh; Chih-Hao Wang; Tsung-Liang Chih; Ya-Hsiu Chi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Cost-Effective Enhancement on Both Yield and Reliability for Cache Designs Based on Performance Degradation Tolerance. - Tong-Yu Hsieh; Tsung-Liang Chih; Mei-Jung Wu (IEEE Trans. Very Large Scale Integr. Syst., 2017)