High speed DDR2/3 PHY and dual CPU core design for 28nm SoC. - Kevin Ho; Tsung-Yi Chou; Po-Kai Chen; David J. Liou (VLSI-DAT, 2012)

A 0.11mm⁁2 150mW 10GBase-T transmitter in 28nm CMOS process. - Tsun-Yuan Fan; Tsung-Yi Chou; Wen-Hua Chang (A-SSCC, 2015)