A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. - Tsung-Yi Wu; Tzu-Chieh Tien; Allen C.-H. Wu; Youn-Long Lin (EDAC-ETC-EUROASIC, 1994)

Storage optimization by replacing some flip-flops with latches. - Youn-Long Lin; Tsung-Yi Wu (EURO-DAC, 1996)

Register minimization beyond sharing among variables. - Tsung-Yi Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A Method of Embedded Memory Access Time Measurement. - Nai-Yin Sung; Tsung-Yi Wu (ISQED, 2001)

A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. - Tsung-Yi Wu; Jr-Luen Tzeng; Kuang-Yao Chen (ASP-DAC, 2007)

A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost. - Tsung-Yi Wu; Jr-Luen Tzeng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

IR Drop Reduction via a Flip-Flop Resynthesis Technique. - Jiun-Kuan Wu; Tsung-Yi Wu; Liang-Ying Lu; Kuang-Yao Chen (ISQED, 2008)

A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates. - How-Rern Lin; Wei-Hao Chiu; Tsung-Yi Wu (IEICE Trans. Electron., 2009)

Low-Leakage and Low-Power Implementation of High-Speed Logic Gates. - Tsung-Yi Wu; Liang-Ying Lu (IEICE Trans. Electron., 2009)

Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs. - Tsung-Yi Wu; Tzi-Wei Kao; Shi-Yi Huang; Tai-Lun Li; How-Rern Lin (ASP-DAC, 2010)

Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs. - Tsung-Yi Wu; Tzi-Wei Kao; How-Rern Lin (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Preliminary Study on Using Augmented Virtuality to Improve Training for Intercollegiate Archers. - Tsung-Yi Wu; Yi-Chieh Chang; Shang-Ti Chen; I-Tsun Chiang (DIGITEL, 2012)

Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM). - Shin-Kai Chen; Chih-Wei Liu; Tsung-Yi Wu; An-Chi Tsai (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Live Demonstration: A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. - Jian-Lin Zeng; Tsung-Yi Wu; Don-Gey Liu; Ching-Hwa Cheng (ISCAS, 2023)

A Low-Power Dual-Core Motion Estimation Chip Design and Validation for a Wireless Panoramic Endoscopy. - Jian-Lin Zeng; Tsung-Yi Wu; Don-Gey Liu; Ching-Hwa Cheng (ISCAS, 2023)