Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. - Hung-Chang Yu; Kai-Chun Lin; Ku-Feng Lin; Chin-Yi Huang; Yu-Der Chih; Tong-Chern Ong; Tsung-Yung Jonathan Chang; Sreedhar Natarajan; Luan C. Tran (ISSCC, 2013)

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Ku-Feng Lin; Yu-Der Chih; Sreedhar Natarajan; Tsung-Yung Jonathan Chang (ISSCC, 2014)

Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chrong Jung Lin; Ku-Feng Lin; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2015)

A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application. - Chia-Fu Lee; Hon-Jarn Lin; Chiu-Wang Lien; Yu-Der Chih; Tsung-Yung Jonathan Chang (A-SSCC, 2017)

11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme. - Shau-Yu Chou; Yu-Shiang Chen; Jun-Hao Chang; Yu-Der Chih; Tsung-Yung Jonathan Chang (ISSCC, 2017)

Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window. - Chien-An Lai; Chung-Cheng Chou; Chi-Hsiang Weng; Zheng-Jun Lin; Pei-Ling Tseng; Chien-Fan Wang; Chih-Chen Wang; Chin-I Su; Wei-Chi Chen; Yu-Cheng Lin; Tong-Chern Ong; Chi Chang; et al. (A-SSCC, 2018)

An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance. - Chung-Cheng Chou; Zheng-Jun Lin; Pei-Ling Tseng; Chih-Feng Li; Chih-Yang Chang; Wei-Chi Chen; Yu-Der Chih; Tsung-Yung Jonathan Chang (ISSCC, 2018)

A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination. - Qing Dong 001; Zhehong Wang; Jongyup Lim; Yiqun Zhang 002; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (ISSCC, 2018)

Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2018)

A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM. - Kaiyuan Yang 001; Qing Dong 001; Zhehong Wang; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (VLSI Circuits, 2018)

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination. - Qing Dong 001; Zhehong Wang; Jongyup Lim; Yiqun Zhang 002; Mahmut E. Sinangil; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2019)

Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $ mu$ A Sensing Resolution, and 17.5-nS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2019)

13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference. - Yu-Der Chih; Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Chieh-Pu Lo; Meng-Chun Shih; Kuei-Hung Shen; Harry Chuang; Tsung-Yung Jonathan Chang (ISSCC, 2020)

A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range. - Chung-Cheng Chou; Zheng-Jun Lin; Chien-An Lai; Chin-I Su; Pei-Ling Tseng; Wei-Chi Chen; Wu-Chin Tsai; Wen-Ting Chu; Tong-Chern Ong; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2020)

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM. - Zhehong Wang; Ziyun Li; Li Xu 006; Qing Dong 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; David T. Blaauw (VLSI Circuits, 2020)

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. - Yu-Der Chih; Po-Hao Lee; Hidehiro Fujiwara; Yi-Chun Shih; Chia-Fu Lee; Rawan Naous; Yu-Lin Chen; Chieh-Pu Lo; Cheng-Han Lu; Haruki Mori; Wei-Cheng Zhao; Dar Sun; et al. (ISSCC, 2021)

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices. - Cheng-Xin Xue; Je-Min Hung; Hui-Yao Kao; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Peng Chen; Ta-Wei Liu; Chuan-Jia Jhang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; et al. (ISSCC, 2021)

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (IEEE J. Solid State Circuits, 2021)

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator. - Ziyun Li; Zhehong Wang; Li Xu 006; Qing Dong 001; Bowen Liu 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; et al. (IEEE J. Solid State Circuits, 2021)

A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations. - Yen-Cheng Chiu; Chia-Sheng Yang; Shih-Hsih Teng; Hsiao-Yu Huang; Fu-Chun Chang; Yuan Wu 009; Yu-An Chien; Fang-Ling Hsieh; Chung-Yuan Li; Guan-Yi Lin; Po-Jung Chen; Tsen-Hsiang Pan; et al. (ISSCC, 2022)

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Mei-Chen Chuang; Rawan Naous; Chao-Kai Chuang; Takeshi Hashizume; Dar Sun; Chia-Fu Lee; Kerem Akarvardar; Saman Adham; Tan-Li Chou; et al. (ISSCC, 2022)

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. - Je-Min Hung; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Tai-Hao Wen; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (ISSCC, 2022)

A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. - Chia-Fu Lee; Cheng-Han Lu; Cheng-En Lee; Haruki Mori; Hidehiro Fujiwara; Yi-Chun Shih; Tan-Li Chou; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2022)

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device. - Yen-Cheng Chiu; Tung-Cheng Chang; Chun-Ying Lee; Je-Min Hung; Kuang-Tang Chang; Cheng-Xin Xue; Ssu-Yen Wu; Hui-Yao Kao; Peng Chen; Hsiao-Yu Huang; Shih-Hsih Teng; Chieh-Pu Lo; et al. (IEEE J. Solid State Circuits, 2022)

A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices. - Yen-Cheng Chiu; Win-San Khwa; Chung-Yuan Li; Fang-Ling Hsieh; Yu-An Chien; Guan-Yi Lin; Po-Jung Chen; Tsen-Hsiang Pan; De-Qi You; Fang-Yi Chen; Andrew Lee; Chung-Chuan Lo; et al. (ISSCC, 2023)

A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. - Wei-Hsing Huang; Tai-Hao Wen; Je-Min Hung; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Hung-Hsi Hsu; Yu-Hsiang Chin; Yu-Chiao Chen; Chuna-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; et al. (ISSCC, 2023)

A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity. - Po-Hao Lee; Chia-Fu Lee; Yi-Chun Shih; Hon-Jarn Lin; Yen-An Chang; Cheng-Han Lu; Yu-Lin Chen; Chieh-Pu Lo; Chung-Chieh Chen; Cheng-Hsiung Kuo; Tan-Li Chou; Chia-Yu Wang; et al. (ISSCC, 2023)

A 4nm 6163-TOPS/W/b $ mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. - Haruki Mori; Wei-Chang Zhao; Cheng-En Lee; Chia-Fu Lee; Yu-Hao Hsu; Chao-Kai Chuang; Takeshi Hashizume; Hao-Chun Tung; Yao-Yi Liu; Shin-Rung Wu; Kerem Akarvardar; Tan-Li Chou; et al. (ISSCC, 2023)

A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. - Yumito Aoyagi; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. - Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Jhon-Jhy Liaw; Shien-Yang Michael Wu; Quincy Li; Hidehiro Fujiwara; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. - Tai-Hao Wen; Je-Min Hung; Hung-Hsi Hsu; Yuan Wu 009; Fu-Chun Chang; Chung-Yuan Li; Chih-Han Chien; Chin-I Su; Win-San Khwa; Jui-Jen Wu; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2023)

Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs. - Wei-Xiang You; Cheng-Yin Wang; Yih Wang; Tsung-Yung Jonathan Chang; Szuya Sandy Liao (VLSI Technology and Circuits, 2023)

A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology. - Nick Zhang; Young Suk Kim; Peter Hsu; Samsoo Kim; Derek Tao; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. - Je-Min Hung; Tai-Hao Wen; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (IEEE J. Solid State Circuits, 2023)

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Kinshuk Khare; Cheng-En Lee; Xiaochen Peng; Vineet Joshi; Chao-Kai Chuang; Shu-Huan Hsu; Takeshi Hashizume; Toshiaki Naganuma; Chen-Hung Tien; et al. (ISSCC, 2024)

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (ISSCC, 2024)

15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C. - Yi-Cheng Huang; Shang-Hsuan Liu; Hsu-Shun Chen; Hsin-Chang Feng; Chih-Feng Li; Chou-Ying Yang; Wei-Keng Chang; Chang-Feng Yang; Chun-Yu Wu; Yen-Cheng Lin; Tsung-Tse Yang; Chih-Yang Chang; et al. (ISSCC, 2024)

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes. - Ku-Feng Lin; Hiroki Noguchi; Yi-Chun Shih; Perng-Fei Yuh; Yuan-Jen Lee; Tung-Cheng Chang; Sheng-Po Huang; Yu-Fan Lin; Chun-Ying Lee; Yen-Hsiang Huang; Jui-Che Tsai; Saman Adham; et al. (ISSCC, 2024)

34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. - Tai-Hao Wen; Hung-Hsi Hsu; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; et al. (ISSCC, 2024)

A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. - Ming-Chieh Huang; Wei Wing Mar; Shankar Kanade; Boris Bai; Aditya Gayatri; Krishna Khairnar; Amy Lai; Yu-Hao Hsu; Hung-Jen Liao; Yih Wang; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. - Tomotaka Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Yumito Aoyagi; Masaya Hamada; Kazuto Mizutani; Koji Nii; Hidehiro Fujiwara; Isabel Wang; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. - De-Qi You; Win-San Khwa; Jui-Jen Wu; Chuan-Jia Jhang; Guan-Yi Lin; Po-Jung Chen; Ting-Chien Chiu; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2024)

A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. - Hung-Hsi Hsu; Tai-Hao Wen; Wei-Hsing Huang; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Yu-Hsiang Chin; Yu-Chiao Chen; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (IEEE J. Solid State Circuits, 2024)

An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices. - De-Qi You; Yen-Cheng Chiu; Win-San Khwa; Chung-Yuan Li; Fang-Ling Hsieh; Yu-An Chien; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; Tsung-Yung Jonathan Chang; et al. (IEEE J. Solid State Circuits, 2024)

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. - Yumito Aoyagi; Koji Nii; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2024)

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. - Xiaoyu Sun 001; Weidong Cao 001; Brian Crafton; Kerem Akarvardar; Haruki Mori; Hidehiro Fujiwara; Hiroki Noguchi; Yu-Der Chih; Meng-Fan Chang; Yih Wang; Tsung-Yung Jonathan Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)

29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme. - Hidehiro Fujiwara; Wei-Chang Zhao; Kinshuk Khare; Yi-Hsin Nien; Chih-Yu Lin; Cheng-Han Lin; Shan-Ru Liao; Kenta Torigoe; Shirleen Xia; Yuichiro Ishii; Yao-Yi Lin; Jhon-Jhy Liaw; et al. (ISSCC, 2025)

14.1 A 22nm 104.5TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks. - De-Qi You; Win-San Khwa; Bo Zhang; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Yi-Ming Li; Yu-Hui Wang; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (ISSCC, 2025)

A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)

A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device. - Hung-Hsi Hsu; Tai-Hao Wen; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Ashwin Sanjay Lele; Bo Zhang; Ping-Sheng Wu; et al. (IEEE J. Solid State Circuits, 2025)

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications. - Yoshiaki Osada; Takaaki Nakazato; Yumito Aoyagi; Koji Nii; Jhon-Jhy Liaw; Shien-Yang Wu; Quincy Li; Hidehiro Fujiwara; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)