A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's. - Hiroyuki Yamauchi; Toshikazu Suzuki; Akihiro Sawada; Tohru Iwata; Toshiaki Tsuji; Masashi Agata; Takashi Taniguchi; Yoshinori Odake; Kazuyuki Sawada; Teruhito Ohnishi; Masanori Fukumoto; Tsutomu Fujita; et al. (IEEE J. Solid State Circuits, 1993)

A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures. - Hisakazu Kotani; Hironori Akamatsu; Yasushi Naito; Toyokazu Fujii; Tohru Iwata; Toshiaki Tsuji; Yutaka Itoh; Norisato Shimizu; Junji Hirase; Yoshiyuki Shibata; Kazuhiro Yamashita; Takashi Hori; et al. (IEEE J. Solid State Circuits, 1994)

An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. - Hiroyuki Yamauchi; Hironori Akamatsu; Tsutomu Fujita (IEEE J. Solid State Circuits, 1995)

A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current. - Hiroyuki Yamauchi; Tom Iwata; Akito Uno; Masanori Fukumoto; Tsutomu Fujita (IEEE J. Solid State Circuits, 1995)

A unity power factor PWM rectifier with DC ripple compensation. - Toshihisa Shimizu; Tsutomu Fujita; Gunji Kimura; Jun Hirose (IEEE Trans. Ind. Electron., 1997)

An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D2/RAM). - Yasuhiro Agata; Kenji Motomochi; Yoshifumi Fukushima; Masanori Shirahama; Marefusa Kurumada; Naoki Kuroda; Hiroyuki Sadakata; Kohtaro Hayashi; Toshio Yamada; Kazunari Takahashi; Tsutomu Fujita (IEEE J. Solid State Circuits, 2000)

Toward Introduction of Immunity-based Model to Continuous Behavior-based User Authentication on Smart Phone. - Yuji Watanabe; Houryu; Tsutomu Fujita (KES, 2013)