A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator. - Tomoaki Yabe; Shinji Miyano; Katsuhiko Sato; Masaharu Wada; Ryo Haga; Osamu Wada; Motohiro Enkaku; Takehiko Hojyo; Kenichiro Mimoto; Masaaki Tazawa; Tsutomu Ohkubo; Kenji Numata (IEEE J. Solid State Circuits, 1998)

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus. - Toshimasa Namekawa; Shinji Miyano; Ryo Fukuda; Ryo Haga; Osamu Wada; Hironori Banba; Satoru Takeda; Kazuhiro Suda; Kenichiro Mimoto; Satoshi Yamaguchi; Tsutomu Ohkubo; Hiroshi Takato; et al. (IEEE J. Solid State Circuits, 2000)

Interface socket design methodology to generate embedded DRAM macros. - Ryo Haga; Tetsuya Kaneko; Atsushi Nakayama; Shinji Miyano; Hiroyuki Takenaka; Kenji Numata; Hiroyuki Koinuma; Takehiko Hojo; Akikuni Sato; Toshiyuki Kouchi; Kenichiro Mimoto; Masaaki Tazawa; et al. (CICC, 2001)