Easily Testable Sequential Machines with Extra Inputs. - Hideo Fujiwara; Yoich Nagao; Tsutomu Sasao; Kozo Kinoshita (IEEE Trans. Computers, 1975)

On Magnetic Bubble Logic Circuits. - Kozo Kinoshita; Tsutomu Sasao; Jun Matsuda (IEEE Trans. Computers, 1976)

An application of multiple-valued logic to a design of programmable logic arrays. - Tsutomu Sasao (MVL, 1978)

Realization of Minimum Circuits with Two-Input Conservative Logic Elements. - Tsutomu Sasao; Kozo Kinoshita (IEEE Trans. Computers, 1978)

Cascade Realization of 3-Input 3-Output Conservative Logic Circuits. - Tsutomu Sasao; Kozo Kinoshita (IEEE Trans. Computers, 1978)

Conservative Logic Elements and Their Universality. - Tsutomu Sasao; Kozo Kinoshita (IEEE Trans. Computers, 1979)

On the Number of Fanout-Free Functions and Unate Cascade Functions. - Tsutomu Sasao; Kozo Kinoshita (IEEE Trans. Computers, 1979)

Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays. - Tsutomu Sasao (IEEE Trans. Computers, 1981)

Input Variable Assignment and Output Phase Optimization of PLA's. - Tsutomu Sasao (IEEE Trans. Computers, 1984)

An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs. - Tsutomu Sasao (IEEE Trans. Computers, 1985)

MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators. - Tsutomu Sasao (DAC, 1986)

Multiple-Valued Logic and Optimization of Programmable Logic Arrays. - Tsutomu Sasao (Computer, 1988)

On the Optimal Design of Multiple-Valued PLA's. - Tsutomu Sasao (IEEE Trans. Computers, 1989)

EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions. - Tsutomu Sasao (ISMVL, 1990)

A Transformation of Multiple-Valued Input Two-Valued Output Functions and its Application to Simplification of Exclusive-or Sum-of-Products Expressions. - Tsutomu Sasao (ISMVL, 1991)

Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions. - Tsutomu Sasao (IEEE Trans. Computers, 1991)

Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams. - Tsutomu Sasao (ISMVL, 1992)

Four-variable AND-EXOR minimum expressions and their properties. - Norio Koda; Tsutomu Sasao (Syst. Comput. Jpn., 1992)

Minimization of AND-EXOR Expressions Using Rewrite Rules. - Daniel Brand; Tsutomu Sasao (IEEE Trans. Computers, 1993)

EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions. - Tsutomu Sasao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Multiple-Valued Combinational Circuits with Feedback. - Jon T. Butler; Tsutomu Sasao (ISMVL, 1994)

A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. - Tsutomu Sasao; Jon T. Butler (ISMVL, 1994)

Calculation of Reed-Muller-Fourier Coefficients of Multiple-Valued Functions through Multiple-Place Decision Diagrams. - Radomir S. Stankovic; Milena Stankovic; Claudio Moraga; Tsutomu Sasao (ISMVL, 1994)

GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions. - Debatosh Debnath; Tsutomu Sasao (ASP-DAC, 1995)

Planar Multiple-Valued Decision Diagrams. - Tsutomu Sasao; Jon T. Butler (ISMVL, 1995)

Planarity in ROMDD's of Multiple-Valued Symmetric Functions. - Jon T. Butler; J. L. Nowlin; Tsutomu Sasao (ISMVL, 1996)

A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. - Tsutomu Sasao; Jon T. Butler (ISMVL, 1996)

A simplification method for AND-EXOR expressions for multiple-output functions. - Norio Koda; Tsutomu Sasao (Syst. Comput. Jpn., 1996)

An optimization of AND-OR-EXOR three-level networks. - Debatosh Debnath; Tsutomu Sasao (ASP-DAC, 1997)

On properties of Kleene TDDs. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ASP-DAC, 1997)

On Decomposition of Kleene TDDs. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (Asian Test Symposium, 1997)

On the Adders with Minimum Tests. - Seiji Kajihara; Tsutomu Sasao (Asian Test Symposium, 1997)

Ternary Decision Diagrams: Survey. - Tsutomu Sasao (ISMVL, 1997)

Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. - Tsutomu Sasao; Jon T. Butler (ISMVL, 1997)

Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. - Jon T. Butler; David S. Herscovici; Tsutomu Sasao; Robert J. Barton III (IEEE Trans. Computers, 1997)

Easily Testable Realizations for Generalized Reed-Muller Expressions. - Tsutomu Sasao (IEEE Trans. Computers, 1997)

A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks. - Debatosh Debnath; Tsutomu Sasao (ASP-DAC, 1998)

Decision Diagrams for Discrete Functions: Classification and Unified Interpretation. - Radomir S. Stankovic; Tsutomu Sasao (ASP-DAC, 1998)

Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. - Hafiz Md. Hasan Babu; Tsutomu Sasao (ISMVL, 1998)

On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. - Jon T. Butler; Tsutomu Sasao (ISMVL, 1998)

Fast Boolean Matching Under Permutation Using Representative. - Debatosh Debnath; Tsutomu Sasao (ASP-DAC, 1999)

Realization of Regular Ternary Logic Functions. - Yukihiro Iguchi; Munehiro Matsuura; Tsutomu Sasao; Atsumu Iseno (ASP-DAC, 1999)

Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions. - Hafiz Md. Hasan Babu; Tsutomu Sasao (ISMVL, 1999)

Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates. - Debatosh Debnath; Tsutomu Sasao (ISMVL, 1999)

Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions. - Tsutomu Sasao (ISMVL, 1999)

Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions. - Debatosh Debnath; Tsutomu Sasao (ASP-DAC, 2000)

A hardware simulation engine based on decision diagrams (short paper). - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura; Atsumu Iseno (ASP-DAC, 2000)

Three parameters to find functional decompositions. - Tsutomu Sasao; Ken-ichi Kurimoto (ASP-DAC, 2000)

Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. - Hafiz Md. Hasan Babu; Tsutomu Sasao (ISMVL, 2000)

Implementation of Multiple-Output Functions Using PQMDDs. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2000)

On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions. - Tsutomu Sasao (ISMVL, 2000)

Selection of potentially testable path delay faults for test generation. - Atsushi Murakami; Seiji Kajihara; Tsutomu Sasao; Irith Pomeranz; Sudhakar M. Reddy (ITC, 2000)

On the minimization of SOPs for bi-decomposition functions. - Tsutomu Sasao; Jon T. Butler (ASP-DAC, 2001)

Realization of Multiple-Output Functions by Reconfigurable Cascades. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ICCD, 2001)

Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic. - Tsutomu Sasao (ISMVL, 2001)

Worst and Best Irredundant Sum-of-Products Expressions. - Tsutomu Sasao; Jon T. Butler (IEEE Trans. Computers, 2001)

A discussion on the history of research in arithmetic andReed-Muller expressions. - Radomir S. Stankovic; Tsutomu Sasao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Representations of Logic Functions Using QRMDDs. - Shinobu Nagayama; Tsutomu Sasao; Yukihiro Iguchi; Munehiro Matsuura (ISMVL, 2002)

Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. - Alan Mishchenko; Tsutomu Sasao (IWLS, 2002)

Comparison of Decision Diagrams for Multiple-Output Logic Functions. - Tsutomu Sasao; Yukihiro Iguchi; Munehiro Matsuura (IWLS, 2002)

Bi-Partition of Shared Binary Decision Diagrams. - Munehiro Matsuura; Tsutomu Sasao; Jon T. Butler; Yukihiro Iguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Evaluation of multiple-output logic functions using decision diagrams. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ASP-DAC, 2003)

Large-scale SOP minimization using decomposition and functional properties. - Alan Mishchenko; Tsutomu Sasao (DAC, 2003)

On the Average Path Length in Decision Diagrams of Multiple-Valued Functions. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2003)

Cascade Realizations of Two-valued Input Multiple-Valued Output Functions using Decomposition of Group Functions. - Tsutomu Sasao (ISMVL, 2003)

Compact Representations of Logic Functions Using Heterogeneous MDDs. - Shinobu Nagayama; Tsutomu Sasao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Efficient computation of canonical form for Boolean matching in large libraries. - Debatosh Debnath; Tsutomu Sasao (ASP-DAC, 2004)

Minimization of memory size for heterogeneous MDDs. - Shinobu Nagayama; Tsutomu Sasao (ASP-DAC, 2004)

A fast method to derive minimum SOPs for decomposable functions. - Tsutomu Sasao; Jon T. Butler (ASP-DAC, 2004)

A method to decompose multiple-output logic functions. - Tsutomu Sasao; Munehiro Matsuura (DAC, 2004)

A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2004)

On the Minimization of Average Path Lengths for Heterogeneous MDDs. - Shinobu Nagayama; Tsutomu Sasao (ISMVL, 2004)

Fault Diagnosis for RAMs Using Walsh Spectrum. - Atsumu Iseno; Yukihiro Iguchi; Tsutomu Sasao (IEICE Trans. Inf. Syst., 2004)

BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. - Tsutomu Sasao; Munehiro Matsuura (DAC, 2005)

On LUT Cascade Realizations of FIR Filters. - Tsutomu Sasao; Yukihiro Iguchi; Takahiro Suzuki (DSD, 2005)

Programmable Numerical Function Generators: Architectures and Synthesis Method. - Tsutomu Sasao; Shinobu Nagayama; Jon T. Butler (FPL, 2005)

An FPGA design of AES encryption circuit with 128-bit keys. - Hui Qin; Tsutomu Sasao; Yukihiro Iguchi (ACM Great Lakes Symposium on VLSI, 2005)

Hardware to Compute Walsh Coefficients. - Yukihiro Iguchi; Tsutomu Sasao (ISMVL, 2005)

Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem. - Marek A. Perkowski; Tsutomu Sasao; Jong-Hwan Kim; Martin Lukac; Jeff Allen; Stefan Gebauer (ISMVL, 2005)

Radix Converters: Complexity and Implementation by LUT Cascades. - Tsutomu Sasao (ISMVL, 2005)

Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs. - Debatosh Debnath; Tsutomu Sasao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders. - Debatosh Debnath; Tsutomu Sasao (IEICE Trans. Inf. Syst., 2005)

A Design Algorithm for Sequential Circuits Using LUT Rings. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams. - Shinobu Nagayama; Alan Mishchenko; Tsutomu Sasao; Jon T. Butler (J. Multiple Valued Log. Soft Comput., 2005)

Average Path Length of Binary Decision Diagrams. - Jon T. Butler; Tsutomu Sasao; Munehiro Matsuura (IEEE Trans. Computers, 2005)

On the optimization of heterogeneous MDDs. - Shinobu Nagayama; Tsutomu Sasao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Implementation of LPM Address Generators on FPGAs. - Hui Qin; Tsutomu Sasao; Jon T. Butler (ARC, 2006)

Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ASP-DAC, 2006)

A fast logic simulator using a look up table cascade emulator. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ASP-DAC, 2006)

A Soft Error Tolerant LUT Cascade Emulator. - Hiroki Nakahara; Tsutomu Sasao (ATS, 2006)

On Designs of Radix Converters Using Arithmetic Decompositions. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2006)

Design Methods for Multiple-Valued Input Address Generators. - Tsutomu Sasao (ISMVL, 2006)

Implementation of Multiple-Valued CAM Functions by LUT Cascades. - Tsutomu Sasao; Jon T. Butler (ISMVL, 2006)

Representations of Elementary Functions Using Binary Moment Diagrams. - Tsutomu Sasao; Shinobu Nagayama (ISMVL, 2006)

Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries. - Debatosh Debnath; Tsutomu Sasao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA. - Hui Qin; Tsutomu Sasao; Yukihiro Iguchi (IEICE Trans. Inf. Syst., 2006)

Analysis and synthesis of weighted-sum functions. - Tsutomu Sasao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ASP-DAC, 2007)

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (DSD, 2007)

An Implementation of an Address Generator Using Hash Memories. - Tsutomu Sasao; Munehiro Matsuura (DSD, 2007)

Implementations of Reconfigurable Logic Arrays on FPGAs. - Tsutomu Sasao; Hiroki Nakahara (FPT, 2007)

A CAM Emulator Using Look-Up Table Cascades. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IPDPS, 2007)

On Designs of Radix Converters Using Arithmetic Decompositions–Binary to Decimal Converters–. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2007)

Representations of Elementary Functions Using Edge-Valued MDDs. - Shinobu Nagayama; Tsutomu Sasao (ISMVL, 2007)

An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays. - Tsutomu Sasao (ISMVL, 2007)

A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks. - Debatosh Debnath; Tsutomu Sasao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Design Methods of Radix Converters Using Arithmetic Decompositions. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2007)

BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades. - Munehiro Matsuura; Tsutomu Sasao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (J. Multiple Valued Log. Soft Comput., 2007)

Numerical Function Generators Using LUT Cascades. - Tsutomu Sasao; Shinobu Nagayama; Jon T. Butler (IEEE Trans. Computers, 2007)

Programmable Numerical Function Generators for Two-Variable Functions. - Shinobu Nagayama; Jon T. Butler; Tsutomu Sasao (DSD, 2008)

On the Complexity of Error Detection Functions for Redundant Residue Number Systems. - Tsutomu Sasao; Yukihiro Iguchi (DSD, 2008)

Numerical function generators using bilinear interpolation. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (FPL, 2008)

On the numbers of variables to represent sparse logic functions. - Tsutomu Sasao (ICCAD, 2008)

Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators. - Shinobu Nagayama; Tsutomu Sasao (ISMVL, 2008)

On the Complexity of Classification Functions. - Tsutomu Sasao (ISMVL, 2008)

A Parallel Branching Program Machine for Emulation of Sequential Circuits. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (ARC, 2009)

The Parallel Sieve Method for a Virus Scanning Engine. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (DSD, 2009)

Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. - Tsutomu Sasao; Takaaki Nakamura; Munehiro Matsuura (DSD, 2009)

A virus scanning engine using a parallel finite-input memory machine and MPUs. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (FPL, 2009)

Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2009)

A Quaternary Decision Diagram Machine and the Optimization of its Code. - Tsutomu Sasao; Hiroki Nakahara; Munehiro Matsuura; Yoshifumi Kawamura; Jon T. Butler (ISMVL, 2009)

Complexities of Graph-Based Representations for Elementary Functions. - Shinobu Nagayama; Tsutomu Sasao (IEEE Trans. Computers, 2009)

Progress in Applications of Boolean Functions - Tsutomu Sasao; Jon T. Butler (Morgan & Claypool Publishers, 2009)

A Packet Classifier Using a Parallel Branching Program Machine. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (DSD, 2010)

On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions. - Tsutomu Sasao (DSD, 2010)

Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2010)

A Comparison of Architectures for Various Decision Diagram Machines. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2010)

On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables. - Tsutomu Sasao (ISMVL, 2010)

A regular expression matching using non-deterministic finite automaton. - Hiroshi Nakahara; Tsutomu Sasao; Munehiro Matsuura (MEMOCODE, 2010)

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Inf. Syst., 2010)

A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Yoshifumi Kawamura (IEICE Trans. Inf. Syst., 2010)

A Quaternary Decision Diagram Machine: Optimization of Its Code. - Tsutomu Sasao; Hiroki Nakahara; Munehiro Matsuura; Yoshifumi Kawamura; Jon T. Butler (IEICE Trans. Inf. Syst., 2010)

Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

On the number of segments needed in a piecewise linear approximation. - C. L. Frenzen; Tsutomu Sasao; Jon T. Butler (J. Comput. Appl. Math., 2010)

Index to Constant Weight Codeword Converter. - Jon T. Butler; Tsutomu Sasao (ARC, 2011)

A Regular Expression Matching Circuit Based on a Decomposed Automaton. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ARC, 2011)

Fast Hardware Computation of x Mod z. - Jon T. Butler; Tsutomu Sasao (IPDPS Workshops, 2011)

Numeric Function Generators Using Piecewise Arithmetic Expressions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2011)

A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2011)

Index Generation Functions: Recent Developments. - Tsutomu Sasao (ISMVL, 2011)

A fast segmentation algorithm for piecewise polynomial numeric function generators. - Jon T. Butler; C. L. Frenzen; Njuguna Macaria; Tsutomu Sasao (J. Comput. Appl. Math., 2011)

A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ARC, 2012)

Linear decomposition of index generation functions. - Tsutomu Sasao (ASP-DAC, 2012)

Row-shift decompositions for index generation functions. - Tsutomu Sasao (DATE, 2012)

On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer. - Hiroki Nakahara; Hiroyuki Nakanishi; Tsutomu Sasao (ICA3PP (1), 2012)

Hardware Index to Permutation Converter. - Jon T. Butler; Tsutomu Sasao (IPDPS Workshops, 2012)

Analysis of Multi-state Systems with Multi-state Components Using EVMDDs. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2012)

Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2012)

Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation. - Tsutomu Sasao (ISMVL, 2012)

A Fast Head-Tail Expression Generator for TCAM - Application to Packet Classification. - Infall Syafalni; Tsutomu Sasao (ISVLSI, 2012)

A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2012)

A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (Microprocess. Microsystems, 2012)

A Comparison of Multi-Valued and Heterogeneous Decision Diagram Machines. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (J. Multiple Valued Log. Soft Comput., 2012)

On a wideband fast fourier transform for a radio telescope. - Hiroki Nakahara; Hiroyuki Nakanishi; Tsutomu Sasao (SIGARCH Comput. Archit. News, 2012)

Hardware Index to Set Partition Converter. - Jon T. Butler; Tsutomu Sasao (ARC, 2013)

An Architecture for IPv6 Lookup Using Parallel Index Generation Units. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ARC, 2013)

A packet classifier using LUT cascades based on EVMDDS (k). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (FPL, 2013)

A TCAM generator for packet classification. - Infall Syafalni; Tsutomu Sasao (ICCD, 2013)

Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2013)

A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2013)

An Application of Autocorrelation Functions to Find Linear Decompositions for Incompletely Specified Index Generation Functions. - Tsutomu Sasao (ISMVL, 2013)

Four Decades of Multi-Valued Logic: Lists of Highly Cited Papers. - Tsutomu Sasao (ISMVL, 2013)

A Virus Scanning Engine Using an MPU and an IGU Based on Row-Shift Decomposition. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2013)

On the Numbers of Products in Prefix SOPs for Interval Functions. - Infall Syafalni; Tsutomu Sasao (IEICE Trans. Inf. Syst., 2013)

Multiple-Valued Index Generation Functions: Reduction of Variables by Linear Transformation. - Tsutomu Sasao (J. Multiple Valued Log. Soft Comput., 2013)

Soft-error tolerant TCAMs for high-reliability packet classifications. - Infall Syafalni; Tsutomu Sasao; Xiaoqing Wen; Stefan Holst; Kohei Miyase (APCCAS, 2014)

Inadmissible Class of Boolean Functions under Stuck-at Faults. - Debesh K. Das; Debabani Chowdhury; Bhargab B. Bhattacharya; Tsutomu Sasao (ISMVL, 2014)

Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler; Mitchell A. Thornton; Theodore W. Manikas (ISMVL, 2014)

An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2014)

A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions. - Tsutomu Sasao; Yuta Urano; Yukihiro Iguchi (ISMVL, 2014)

On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler; Mitchell A. Thornton; Theodore W. Manikas (IEICE Trans. Inf. Syst., 2014)

A Packet Classifier Based on Prefetching EVMDD (k) Machines. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2014)

A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix. - Tsutomu Sasao; Yuta Urano; Yukihiro Iguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Head-Tail Expressions for Interval Functions. - Infall Syafalni; Tsutomu Sasao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Approach to design a compact reversible low power binary comparator. - Hafiz Md. Hasan Babu; Nazir Saleheen; Lafifa Jamal; Sheikh Muhammad Sarwar; Tsutomu Sasao (IET Comput. Digit. Tech., 2014)

EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (J. Multiple Valued Log. Soft Comput., 2014)

Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (J. Multiple Valued Log. Soft Comput., 2014)

A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura (J. Multiple Valued Log. Soft Comput., 2014)

Index Generation Functions: Tutorial. - Tsutomu Sasao (J. Multiple Valued Log. Soft Comput., 2014)

Applications of Zero-Suppressed Decision Diagrams - Tsutomu Sasao; Jon T. Butler (Morgan & Claypool Publishers, 2014)

A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank. - Hiroki Nakahara; Hideki Yoshida; Shin-ich Shioya; Renji Mikami; Tsutomu Sasao (ARC, 2015)

A soft-error tolerant TCAM using partial don't-care keys. - Infall Syafalni; Tsutomu Sasao; Xiaoqing Wen; Stefan Holst; Kohei Miyase (ETS, 2015)

A deep convolutional neural network based on nested residue number system. - Hiroki Nakahara; Tsutomu Sasao (FPL, 2015)

Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler; Mitchell A. Thornton; Theodore W. Manikas (ISMVL, 2015)

An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD. - Hiroki Nakahara; Tsutomu Sasao; Hiroyuki Nakanishi; Kazumasa Iwai (ISMVL, 2015)

A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min Method. - Tsutomu Sasao (ISMVL, 2015)

A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units. - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Hisashi Iwamoto; Yasuhiro Terao (IEICE Trans. Inf. Syst., 2015)

High-Speed Hardware Partition Generation. - Jon T. Butler; Tsutomu Sasao (ACM Trans. Reconfigurable Technol. Syst., 2015)

A memory-based realization of a binarized deep convolutional neural network. - Hiroki Nakahara; Haruyoshi Yonekawa; Tsutomu Sasao; Hisashi Iwamoto; Masato Motomura (FPT, 2016)

On the Inadmissible Class of Multiple-Valued Faulty-Functions under Stuck-at Faults. - Debabani Chowdhury; Debesh K. Das; Bhargab B. Bhattacharya; Tsutomu Sasao (ISMVL, 2016)

An Efficient Heuristic for Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2016)

An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope. - Hiroki Nakahara; Tsutomu Sasao; Hiroyuki Nakanishi; Kazumasa Iwai; Tohru Nagao; Naoya Ogawa (ISMVL, 2016)

A Realization of Index Generation Functions Using Multiple IGUs. - Tsutomu Sasao (ISMVL, 2016)

Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM. - Infall Syafalni; Tsutomu Sasao; Xiaoqing Wen (ISVLSI, 2016)

A set partition number system. - Jon T. Butler; Tsutomu Sasao (Australas. J Comb., 2016)

LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification. - Hiroki Nakahara; Tsutomu Sasao; Hisashi Iwamoto; Munehiro Matsuura (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k). - Hiroki Nakahara; Tsutomu Sasao; Munehiro Matsuura; Hisashi Iwamoto (J. Multiple Valued Log. Soft Comput., 2016)

An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division. - Hiroki Nakahara; Hiroyuki Nakanishi; Kazumasa Iwai; Tsutomu Sasao (SIGARCH Comput. Archit. News, 2016)

An algorithm to find optimum support-reducing decompositions for index generation functions. - Tsutomu Sasao; Kyu Matsuura; Yukihiro Iguchi (DATE, 2017)

An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2017)

A Random Forest Using a Multi-valued Decision Diagram on an FPGA. - Hiroki Nakahara; Akira Jinguji; Simpei Sato; Tsutomu Sasao (ISMVL, 2017)

Index Generation Functions: Minimization Methods. - Tsutomu Sasao (ISMVL, 2017)

A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Inf. Syst., 2017)

A Fast Updatable Implementation of Index Generation Functions Using Multiple IGUs. - Tsutomu Sasao (IEICE Trans. Inf. Syst., 2017)

A Linear Decomposition of Index Generation Functions: Optimization Using Autocorrelation Functions. - Tsutomu Sasao (J. Multiple Valued Log. Soft Comput., 2017)

Decomposition of Index Generation Functions Using a Monte Carlo Method. - Tsutomu Sasao; Jon T. Butler (Advanced Logic Synthesis, 2018)

A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector. - Hiroki Nakahara; Tsutomu Sasao (ISCAS, 2018)

An Exact Method to Enumerate Decomposition Charts for Index Generation Functions. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2018)

An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2018)

On a Memory-Based Realization of Sparse Multiple-Valued Functions. - Tsutomu Sasao (ISMVL, 2018)

An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (FLAP, 2018)

A Method to Detect Bit Flips in a Soft-Error Resilient TCAM. - Infall Syafalni; Tsutomu Sasao; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya. - Radomir S. Stankovic; Tsutomu Sasao; Jaakko T. Astola; Akihiko Yamada (EUROCAST (1), 2019)

Realizing all Index Generation Functions by the Row-Shift Method. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2019)

Maximally Asymmetric Multiple-Valued Functions. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2019)

A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2019)

On a Minimization of Variables to Represent Sparse Multi-Valued Input Decision Functions. - Tsutomu Sasao (ISMVL, 2019)

Index Generation Functions - Tsutomu Sasao (Morgan & Claypool Publishers, 2019)

Properties of Multiple-Valued Partition Functions. - Jon T. Butler; Tsutomu Sasao; Shinobu Nagayama (ISMVL, 2020)

On Optimum Linear Decomposition of Symmetric Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2020)

On the Minimization of Variables to Represent Partially Defined Classification Functions. - Tsutomu Sasao (ISMVL, 2020)

Handwritten Digit Recognition Based on Classification Functions. - Tsutomu Sasao; Yuto Horikawa; Yukihiro Iguchi (ISMVL, 2020)

Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2021)

Linear Decompositions for Multi-Valued Input Classification Functions. - Tsutomu Sasao; Jon T. Butler (ISMVL, 2021)

A Design Method for Multiclass Classifiers. - Tsutomu Sasao; Yuto Horikawa; Yukihiro Iguchi (ISMVL, 2021)

Classification Functions for Handwritten Digit Recognition. - Tsutomu Sasao; Yuto Horikawa; Yukihiro Iguchi (IEICE Trans. Inf. Syst., 2021)

Realization of Multi-Terminal Universal Interconnection Networks Using Contact Switches. - Tsutomu Sasao; Takashi Matsubara 002; Katsufumi Tsuji; Yoshiaki Koga (IEICE Trans. Inf. Syst., 2021)

On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2022)

On Decision Diagrams for Maximally Asymmetric Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2022)

LUT Cascade Realization of Threshold Functions and Its Application to Implementation of Ternary Weight Neural Networks. - Tsutomu Sasao (ISMVL, 2022)

A Method To Generate Rules From Examples. - Tsutomu Sasao (ISMVL, 2022)

A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (J. Multiple Valued Log. Soft Comput., 2022)

Decomposition-Based Representation of Symmetric Multiple-Valued Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2023)

Data Mining Using Multi-Valued Logic Minimization. - Tsutomu Sasao (ISMVL, 2023)

A Logical Method to Predict Outcomes After Coronary Artery Bypass Grafting. - Tsutomu Sasao; Anders Holmgren; Patrik Eklund (ISMVL, 2023)

On the distribution of sensitivities of symmetric Boolean functions. - Jon T. Butler; Tsutomu Sasao; Shinobu Nagayama (CoRR, 2023)

On Representation of Maximally Asymmetric Functions Based on Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (FLAP, 2023)

Approximate Synthesis for Classification Functions. - Tsutomu Sasao (ISMVL, 2024)

Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Inf. Syst., 2024)

On Easily Reconstructable Logic Functions. - Tsutomu Sasao (IEICE Trans. Inf. Syst., 2024)

Representation of Rotation Symmetric Multiple-Valued Functions Using Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler; Martin Lukac (ISMVL, 2025)

Linear Transformations for Iterative Reduction of Variables. - Tsutomu Sasao (ISMVL, 2025)