A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication. - Tsutomu Yoshimura; Harufusa Kondoh; Yoshio Matsuda; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. - Yasunobu Nakase; Yoshikazu Morooka; David J. Perlman; Daniel J. Kolor; Jae-Myoung Choi; Hyun J. Shin; Tsutomu Yoshimura; Naoya Watanabe; Yoshio Matsuda; Masaki Kumanoya; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)

A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology. - Tsutomu Yoshimura; Kimio Ueda; Jun Takasoh; Yoshiki Wada; Toshihide Oka; Harufusa Kondoh; Osamu Chiba; Yoshihumi Azekawa; Masahiko Ishiwaki (CICC, 2002)

An analysis of interference in synchronous systems. - Tsutomu Yoshimura; Atsushi Iwata (IEICE Electron. Express, 2004)

A study of interference in synchronous systems. - Tsutomu Yoshimura; Atsushi Iwata (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IET Circuits Devices Syst., 2012)

Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. - Tsutomu Yoshimura; Shuhei Iwade; Hiroshi Makino; Yoshio Matsuda (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Analysis and modeling of oscillators with interference noise. - Shinji Shimizu; Junki Mizuno; Shuei Morishita; Koichiro Hida; Tsutomu Yoshimura (ICECS, 2014)

Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. - Shunji Nakata; Hiroshi Makino; Junpei Hosokawa; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Subharmonically injection-locked PLL with variable pulse-width injections. - Shuei Morishita; Shinji Shimizu; Takao Kihara; Tsutomu Yoshimura (ISCAS, 2015)

A study on fast motion estimation algorithm. - Masahiro Hiramori; Ryota Bandou; Shuhei Iwade; Hiroshi Makino; Tsutomu Yoshimura; Yoshio Matsuda (GCCE, 2016)

A 2.6GHz subharmonically injection-locked PLL with low-spur and wide-lock-range injection. - Naohiro Fujii; Shuei Morishita; Takao Kihara; Tsutomu Yoshimura (NEWCAS, 2016)

Analysis and design of differential LNAs with on-chip transformers in 65-nm CMOS technology. - Takao Kihara; Shigesato Matsuda; Tsutomu Yoshimura (NEWCAS, 2016)

Spur reduction by self-injection loop in a fractional-N PLL. - Mayu Kobayashi; Yuya Masui; Takao Kihara; Tsutomu Yoshimura (ICECS, 2017)

Digital correction of mismatches in time-interleaved ADCs for digital-RF receivers. - Tomoya Takahashi; Takao Kihara; Tsutomu Yoshimura (ICECS, 2017)

Design of cascaded integrator-comb decimation filters for direct-RF sampling receivers. - Takao Kihara; Hiroyuki Yano; Tsutomu Yoshimura (ISCAS, 2017)

A Polyphase Decimation Filter for Time-Interleaved ADCs in Direct-RF Sampling Receivers. - Yuma Isobe; Takao Kihara; Tsutomu Yoshimura (APCCAS, 2018)

Study of mutual injection pulling in a 5-GHz, 0.18-μm CMOS cascaded PLL. - Kazuki Miyao; Tatsuya Okafuji; Takao Kihara; Tsutomu Yoshimura (APCCAS, 2018)

A Standard-cell Based A/D Converter with a Back-gate VCO and a Fat Tree Encoder. - Fukuyama Tokuya; Takao Kihara; Tsunehiro Yoshio; Tsutomu Yoshimura (APCCAS, 2018)

A Design of Engineering PBL on Embedded System for Novice Freshmen Students. - Hiroyuki Kobayashi; Kazuo Kumamoto; Tsutomu Yoshimura; Toshio Haga; Muneyoshi Iyota; Makoto Katoh (TENCON, 2018)

Digital Third-Order Nonlinearity Correction for Time-Interleaved A/D Converters with VCOs. - Takao Kihara; Keisuke Miyakoshi; Tsutomu Yoshimura (ISCAS, 2019)

Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling Receivers. - Takao Kihara; Tomoya Takahashi; Tsutomu Yoshimura (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Mitigation of Mutual Pulling in Two Phase-locked Loops. - Tsutomu Yoshimura (NEWCAS, 2021)

Study of Injection Pulling of Oscillators in Phase-Locked Loops. - Tsutomu Yoshimura (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Self-Coupling and Mutual Pulling in Phase-Locked Loops. - Tsutomu Yoshimura (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Analysis of the Electromagnetic Coupling of Two Phase-Locked Loops. - Ryuji Komabayashi; Tsutomu Yoshimura (ISCAS, 2023)