Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (Asian Test Symposium, 2003)

A design methodology to realize delay testable controllers using state transition information. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (ETS, 2004)

Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. - Kazuko Kambe; Michiko Inoue; Hideo Fujiwara; Tsuyoshi Iwagaki (Asian Test Symposium, 2005)

Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (ETS, 2005)

A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (VLSI-SoC, 2006)

Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (VLSI-SoC (Selected Papers), 2006)

A Low Power Deterministic Test Using Scan Chain Disable Technique. - Zhiqiang You; Tsuyoshi Iwagaki; Michiko Inoue; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2006)

Efficient path delay test generation based on stuck-at test generation using checker circuitry. - Tsuyoshi Iwagaki; Satoshi Ohtake; Mineo Kaneko; Hideo Fujiwara (ICCAD, 2007)

Safe clocking register assignment in datapath synthesis. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (ICCD, 2008)

Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Safe clocking for the setup and hold timing constraints in datapath synthesis. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (ACM Great Lakes Symposium on VLSI, 2009)

On the derivation of a minimum test set in high quality transition testing. - Tsuyoshi Iwagaki; Mineo Kaneko (LATW, 2009)

Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties. - Tsuyoshi Iwagaki; Mineo Kaneko (DELTA, 2010)

Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. - Tsuyoshi Iwagaki; Kewal K. Saluja (DDECS, 2011)

Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer. - Tsuyoshi Iwagaki; Eiri Takeda; Mineo Kaneko (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool. - Tsuyoshi Iwagaki; Takehiro Mikami; Hideyuki Ichihara; Tomoo Inoue (APCCAS, 2012)

Modeling economics of LSI design and manufacturing for test design selection. - Hideyuki Ichihara; Noboru Shimizu; Tsuyoshi Iwagaki; Tomoo Inoue (ICCD, 2012)

A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test. - Yuki Fukazawa; Tsuyoshi Iwagaki; Hideyuki Ichihara; Tomoo Inoue (Asian Test Symposium, 2013)

Scheduling algorithm in datapath synthesis for long duration transient fault tolerance. - Tsuyoshi Iwagaki; Tatsuya Nakaso; Ryoko Ohkubo; Hideyuki Ichihara; Tomoo Inoue (DFT, 2014)

Compact and accurate stochastic circuits with shared random number sources. - Hideyuki Ichihara; Shota Ishii; Daiki Sunamori; Tsuyoshi Iwagaki; Tomoo Inoue (ICCD, 2014)

A practical approach for logic simplification based on fault acceptability for error tolerant application. - Hideyuki Ichihara; Junpei Kamei; Tsuyoshi Iwagaki; Tomoo Inoue (ETS, 2015)

Designing area-efficient controllers for multi-cycle transient fault tolerant systems. - Tsuyoshi Iwagaki; Yutaro Ishimori; Hideyuki Ichihara; Tomoo Inoue (ETS, 2015)

Logic simplification by minterm complement for error tolerant application. - Hideyuki Ichihara; Tomoya Inaoka; Tsuyoshi Iwagaki; Tomoo Inoue (ICCD, 2015)

State assignment for fault tolerant stochastic computing with linear finite state machines. - Hideyuki Ichihara; Motoi Fukuda; Tsuyoshi Iwagaki; Tomoo Inoue (ITC-Asia, 2017)

State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines. - Hideyuki Ichihara; Yuki Maeda; Tsuyoshi Iwagaki; Tomoo Inoue (DFT, 2019)

An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis. - Tsuyoshi Iwagaki; Sho Yuasa; Hideyuki Ichihara; Tomoo Inoue (ITC-Asia, 2019)

Compact and Accurate Digital Filters Based on Stochastic Computing. - Hideyuki Ichihara; Tatsuyoshi Sugino; Shota Ishii; Tsuyoshi Iwagaki; Tomoo Inoue (IEEE Trans. Emerg. Top. Comput., 2019)

Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines. - Hideyuki Ichihara; Motoi Fukuda; Tsuyoshi Iwagaki; Tomoo Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)