A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. - Masafumi Takahashi; Mototsugu Hamada; Tsuyoshi Nishikawa; Hideho Arakida; Tetsuya Fujita; Fumitoshi Hatori; Shinji Mita; Kojiro Suzuki; Akihiko Chiba; Toshihiro Terazawa; Fumihiko Sano; Yoshinori Watanabe; et al. (IEEE J. Solid State Circuits, 1998)

A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications. - Masafumi Takahashi; Tsuyoshi Nishikawa; Hideho Arakida; Noriaki Machida; Hideaki Yamamoto; Toshihide Fujiyoshi; Yoko Matsumoto; Osamu Yamagishi; Tatsuo Samata; Atsushi Asano; Toshihiro Terazawa; Kenji Ohmori; et al. (ISCAS, 2000)

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. - Masafumi Takahashi; Tsuyoshi Nishikawa; Mototsugu Hamada; Toshinari Takayanagi; Hideho Arakida; Noriaki Machida; Hideaki Yamamoto; Toshihide Fujiyoshi; Yoko Ohashi; Osamu Yamagishi; Tatsuo Samata; Atsushi Asano; et al. (IEEE J. Solid State Circuits, 2000)

A Single-Chip Low-Power Mpeg-4 Audiovisual Lsi Using Embedded Dram Technology. - Masafumi Takahashi; Tsuyoshi Nishikawa; Hideho Arakida; Tohru Furuyama (ICME, 2001)

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. - Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Chen Kong Teh; Takayoshi Shimazawa; Naoyuki Kawabe; Takeshi Kitahara; Yu Kikuchi; Tsuyoshi Nishikawa; Makoto Takahashi; Yukihito Oowaki (CICC, 2005)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)

An automated runtime power-gating scheme. - Mototsugu Hamada; Takeshi Kitahara; Naoyuki Kawabe; Hironori Sato; Tsuyoshi Nishikawa; Takayoshi Shimazawa; Takahiro Yamashita; Hiroyuki Hara; Yukihito Oowaki (ICCD, 2007)