Incremental layout placement modification algorithms. - Chiu-sing Choy; Tsz-Shing Cheung; Kam-Keung Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

500-Mb/s nonprecharged data bus for high-speed DRAM's. - Miyoshi Saito; Junji Ogawa; Hirotaka Tamura; Shigetoshi Wakayama; Hisakatsu Araki; Tsz-Shing Cheung; Kohtaroh Gotoh; Tadao Aikawa; Takaaki Suzuki; Masao Taguchi; Takeshi Imamura (IEEE J. Solid State Circuits, 1998)

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. - Yusuke Okaniwa; Hirotaka Tamura; Masaya Kibune; Daisuke Yamazaki; Tsz-Shing Cheung; Junji Ogawa; Nestoras Tzartzanis; William W. Walker; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)