A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection. - Duy Thanh Nguyen; Tuan Nghia Nguyen 002; Hyun Kim 001; Hyuk-Jae Lee (IEEE Trans. Very Large Scale Integr. Syst., 2019)

ShortcutFusion: From Tensorflow to FPGA-based accelerator with reuse-aware memory allocation for shortcut data. - Duy Thanh Nguyen; Hyeonseung Je; Tuan Nghia Nguyen 002; Soojung Ryu; Kyujung Lee; Hyuk-Jae Lee (CoRR, 2021)

A Real-time Super-resolution Accelerator Using a big. LITTLE Core Architecture. - Xuan Truong Nguyen; Tuan Nghia Nguyen 002; Hyuk-Jae Lee; Kyujoong Lee (AICAS, 2022)

Computation-Skipping Mask Generation for Super-Resolution Networks. - Tuan Nghia Nguyen 002; Xuan Truong Nguyen; Kyujoong Lee; Hyuk-Jae Lee (ICEIC, 2022)

ShortcutFusion: From Tensorflow to FPGA-Based Accelerator With a Reuse-Aware Memory Allocation for Shortcut Data. - Duy Thanh Nguyen; Hyeonseung Je; Tuan Nghia Nguyen 002; Soojung Ryu; Kyujoong Lee; Hyuk-Jae Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Eight-bit Quantization for Super-Resolution Networks and Its Hardware Implementation. - Xuan Truong Nguyen; Younghoon Ko; Tuan Nghia Nguyen 002; Hyuk-Jae Lee; Kyujoong Lee (ICEIC, 2023)

Accelerating Super-Resolution Network Inference via Sensitivity-Based Weight Sparsity Allocation. - Tuan Nghia Nguyen 002; Xuan Truong Nguyen; Kyujoong Lee; Hyuk-Jae Lee (IEEE Access, 2023)

ENAF: A Multi-Exit Network with an Adaptive Patch Fusion for Large Image Super Resolution. - Manh Duong Nguyen; Tuan Nghia Nguyen 002; Xuan Truong Nguyen (WACV, 2025)