A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS. - Chun-Yu Lin 002; Tun-Ju Wang; Tsung-Hsien Lin (A-SSCC, 2017)

An ultra-low power 169-nA 32.768-kHz fractional-N PLL. - Chun-Yu Lin 002; Tun-Ju Wang; Tzu-Hsuan Liu; Tsung-Hsien Lin (A-SSCC, 2017)

A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique. - Chun-Yu Lin 002; Tun-Ju Wang; Yu-Ting Hung; Tsung-Hsien Lin (VLSI-DAT, 2020)

29.5 A 0.008mm2 1.5mW 0.625-to-200MHz Fractional Output Divider with 120fsrms Jitter Based on Replica-DTC-Free Background Calibration. - Chun-Yu Lin 002; Yu-Ting Hung; Tun-Ju Wang; Tsung-Hsien Lin (ISSCC, 2021)

An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration. - Chun-Yu Lin; Wei-Han Chen; Yu-Ting Hung; Tun-Ju Wang; Tsung-Hsien Lin (IEEE J. Solid State Circuits, 2024)