SoC test scheduling using the B-tree based floorplanning technique. - Jen-Yi Wuu; Tung-Chieh Chen; Yao-Wen Chang (ASP-DAC, 2005)

IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. - Tung-Chieh Chen; Yao-Wen Chang; Shyh-Chang Lin (ICCAD, 2005)

Modern floorplanning based on fast simulated annealing. - Tung-Chieh Chen; Yao-Wen Chang (ISPD, 2005)

NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. - Tung-Chieh Chen; Tien-Chang Hsu; Zhe-Wei Jiang; Yao-Wen Chang (ISPD, 2005)

A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. - Tung-Chieh Chen; Zhe-Wei Jiang; Tien-Chang Hsu; Hsin-Chen Chen; Yao-Wen Chang (ICCAD, 2006)

NTUplace2: a hybrid placer using partitioning and analytical techniques. - Zhe-Wei Jiang; Tung-Chieh Chen; Tien-Chang Hsu; Hsin-Chen Chen; Yao-Wen Chang (ISPD, 2006)

Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. - Tung-Chieh Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs. - Tung-Chieh Chen; Zhe-Wei Jiang; Tien-Chang Hsu; Hsin-Chen Chen; Yao-Wen Chang (Modern Circuit Placement, 2007)

MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. - Tung-Chieh Chen; Ping-Hung Yuh; Yao-Wen Chang; Fwu-Juh Huang; Denny Liu (DAC, 2007)

X-architecture placement based on effective wire models. - Tung-Chieh Chen; Yi-Lin Chuang; Yao-Wen Chang (ISPD, 2007)

An integrated nonlinear placement framework with congestion and porosity aware buffer planning. - Tung-Chieh Chen; Ashutosh Chakraborty; David Z. Pan (DAC, 2008)

Effective Wire Models for X-Architecture Placement. - Tung-Chieh Chen; Yi-Lin Chuang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. - Tung-Chieh Chen; Yao-Wen Chang; Shyh-Chang Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Metal-Density-Driven Placement for CMP Variation and Routability. - Tung-Chieh Chen; Minsik Cho; David Z. Pan; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. - Tung-Chieh Chen; Zhe-Wei Jiang; Tien-Chang Hsu; Hsin-Chen Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. - Tung-Chieh Chen; Ping-Hung Yuh; Yao-Wen Chang; Fwu-Juh Huang; Tien-Yueh Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Packing Floorplan Representations. - Tung-Chieh Chen; Yao-Wen Chang (Handbook of Algorithms for Physical Design Automation, 2008)

Essential Issues in Analytical Placement Algorithms. - Yao-Wen Chang; Zhe-Wei Jiang; Tung-Chieh Chen (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Fast analog layout prototyping for nanometer design migration. - Yi-Peng Weng; Hung-Ming Chen; Tung-Chieh Chen; Po-Cheng Pan; Chien-Hung Chen; Wei-Zen Chen (ICCAD, 2011)

Automated placement for custom digital designs. - Tung-Chieh Chen (ISPD, 2011)

Performance-driven analog placement considering monotonic current paths. - Po-Hsun Wu; Mark Po-Hung Lin; Yang-Ru Chen; Bing-Shiun Chou; Tung-Chieh Chen; Tsung-Yi Ho; Bin-Da Liu (ICCAD, 2012)

Challenges and solutions in modern analog placement. - Tung-Chieh Chen; Ta-Yu Kuan; Chung-Che Hsieh; Chi-Chen Peng (VLSI-DAT, 2012)

Double patterning lithography-aware analog placement. - Hsing-Chih Chang Chien; Hung-Chih Ou; Tung-Chieh Chen; Ta-Yu Kuan; Yao-Wen Chang (DAC, 2013)

Routability-driven placement for hierarchical mixed-size circuit designs. - Meng-Kai Hsu; Yi-Fang Chen; Chau-Chin Huang; Tung-Chieh Chen; Yao-Wen Chang (DAC, 2013)

Lithography-aware 1-dimensional cell generation. - Po-Hsun Wu; Mark Po-Hung Lin; Tung-Chieh Chen; Tsung-Yi Ho; Yu-Chuan Chen (ECCTD, 2013)

Efficient analog layout prototyping by layout reuse with routing preservation. - Ching-Yu Chin; Po-Cheng Pan; Hung-Ming Chen; Tung-Chieh Chen; Jou-Chun Lin (ICCAD, 2013)

1-D Cell Generation With Printability Enhancement. - Po-Hsun Wu; Mark Po-Hung Lin; Tung-Chieh Chen; Tsung-Yi Ho; Yu-Chuan Chen; Shun-Ren Siao; Shu-Hung Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. - Meng-Kai Hsu; Yi-Fang Chen; Chau-Chin Huang; Sheng Chou; Tzu-Hen Lin; Tung-Chieh Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement. - Po-Hsun Wu; Mark Po-Hung Lin; Tung-Chieh Chen; Ching-Feng Yeh; Tsung-Yi Ho; Bin-Da Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

An approach to anchoring and placing high performance custom digital designs. - Shih-Ying Liu; Tung-Chieh Chen; Hung-Ming Chen (ASP-DAC, 2015)

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation. - Po-Cheng Pan; Ching-Yu Chin; Hung-Ming Chen; Tung-Chieh Chen; Chin-Chieh Lee; Jou-Chun Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise. - Po-Hsun Wu; Mark Po-Hung Lin; Tung-Chieh Chen; Ching-Feng Yeh; Xin Li 001; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A novel damped-wave framework for macro placement. - Chin-Hao Chang; Yao-Wen Chang; Tung-Chieh Chen (ICCAD, 2017)

An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. - Szu-To Chen; Yao-Wen Chang; Tung-Chieh Chen (ICCAD, 2017)

Blockage-aware terminal propagation for placement wirelength minimization. - Sheng-Wei Yang; Yao-Wen Chang; Tung-Chieh Chen (ICCAD, 2017)

FastPass: Fast timing path search for generalized timing exception handling. - Pei-Yu Lee; Iris Hui-Ru Jiang; Tung-Chieh Chen (ASP-DAC, 2018)

NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. - Chau-Chin Huang; Hsin-Ying Lee; Bo-Qiao Lin; Sheng-Wei Yang; Chin-Hao Chang; Szu-To Chen; Yao-Wen Chang; Tung-Chieh Chen; Ismail Bustany (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. - Yen-Chun Liu; Tung-Chieh Chen; Yao-Wen Chang; Sy-Yen Kuo (ASP-DAC, 2019)

Automatic Floorplanning for AI SoCs. - Tai-Chen Chen; Pei-Yu Lee; Tung-Chieh Chen (VLSI-DAT, 2020)

VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. - Yun Chou; Jhih-Wei Hsu; Yao-Wen Chang; Tung-Chieh Chen (DAC, 2021)

Flexible chip placement via reinforcement learning: late breaking results. - Fu-Chieh Chang 001; Yu-Wei Tseng; Ya-Wen Yu; Ssu-Rui Lee; Alexandru Cioba; I-Lun Tseng; Da-Shan Shiu; Jhih-Wei Hsu; Cheng-Yuan Wang; Chien-Yi Yang; Ren-Chu Wang; Yao-Wen Chang; et al. (DAC, 2022)

Flexible Multiple-Objective Reinforcement Learning for Chip Placement. - Fu-Chieh Chang 001; Yu-Wei Tseng; Ya-Wen Yu; Ssu-Rui Lee; Alexandru Cioba; I-Lun Tseng; Da-Shan Shiu; Jhih-Wei Hsu; Cheng-Yuan Wang; Chien-Yi Yang; Ren-Chu Wang; Yao-Wen Chang; et al. (CoRR, 2022)

Accurate Estimation of Buffered Interconnect Delay Based on Virtual Buffering and Multi-Level Cluster Tree Techniques. - Chen-Ho Chen; Chien-Nan Jimmy Liu; Wei-Ting Tu; Tung-Chieh Chen; Iris Hui-Ru Jiang (APCCAS, 2024)

Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. - Yu-Yang Chen; Yi-Chen Lin; Tzu-Han Hsu; Iris Hui-Ru Jiang; Tung-Chieh Chen; Tai-Chen Chen; Hua-Yu Chang (ICCAD, 2024)

Introduction to the Panel on EDA Challenges at Advanced Technology Nodes. - Tung-Chieh Chen (ISPD, 2024)

CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs. - Jingyu Pan; Isaac Jacobson; Zheng Zhao; Tung-Chieh Chen; Guanglei Zhou; Chen-Chia Chang; Vineet Rashingkar; Yiran Chen 001 (CoRR, 2025)