Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile. - Wei-Min Chao; Tung-Chien Chen; Yung-Chi Chang; Chih-Wei Hsu; Liang-Gee Chen (ISCAS (2), 2003)

Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC. - Tung-Chien Chen; Yu-Wen Huang; Liang-Gee Chen (ICASSP (5), 2004)

Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture. - Tung-Chien Chen; Yu-Wen Huang; Liang-Gee Chen (ISCAS (2), 2004)

Hardware architecture design for H.264/AVC intra frame coder. - Yu-Wen Huang; Bing-Yu Hsieh; Tung-Chien Chen; Liang-Gee Chen (ISCAS (2), 2004)

Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. - To-Wei Chen; Yu-Wen Huang; Tung-Chien Chen; Yu-Han Chen; Chuan-Yung Tsai; Liang-Gee Chen (ISCAS (3), 2005)

Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. - Tung-Chien Chen; Yu-Wen Huang; Chuan-Yung Tsai; Chao-Tsung Huang; Liang-Gee Chen (ISCAS (2), 2005)

Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder. - Yu-Wen Huang; Bing-Yu Hsieh; Tung-Chien Chen; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2005)

Hardware architecture design of an H.264/AVC video codec. - Tung-Chien Chen; Chung-Jr Lian; Liang-Gee Chen (ASP-DAC, 2006)

Architecture Design of Low Power Integer Motion Estimation for H. 264/AVC. - Tung-Chien Chen; Yu-Han Chen; Sung-Fang Tsai; Liang-Gee Chen (ICASSP (3), 2006)

Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application. - Yu-Han Chen; Tung-Chien Chen; Liang-Gee Chen (ICME, 2006)

Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder. - Chuan-Yung Tsai; Tung-Chien Chen; Liang-Gee Chen (ICME, 2006)

Low power and power aware fractional motion estimation of H.264/AVC for mobile applications. - Tung-Chien Chen; Yu-Han Chen; Chuan-Yung Tsai; Liang-Gee Chen (ISCAS, 2006)

Analysis and architecture design of variable block-size motion estimation for H.264/AVC. - Ching-Yeh Chen; Shao-Yi Chien; Yu-Wen Huang; Tung-Chien Chen; Tu-Chih Wang; Liang-Gee Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC. - Tung-Chien Chen; Yu-Wen Huang; Chuan-Yung Tsai; Bing-Yu Hsieh; Liang-Gee Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder. - Tung-Chien Chen; Shao-Yi Chien; Yu-Wen Huang; Chen-Han Tsai; Ching-Yeh Chen; To-Wei Chen; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2006)

Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System. - Chuan-Yuan Tsai; Chen-Han Chung; Yu-Han Chen; Tung-Chien Chen; Liang-Gee Chen (ICASSP (2), 2007)

System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint. - Pei-Kuei Tsung; Li-Fu Ding; Wei-Yin Chen; Shao-Yi Chien; Tung-Chien Chen; Liang-Gee Chen (ISCAS, 2007)

Reconfigurable architecture for video applications. - Chung-Jr Lian; Po-Chih Tseng; Tung-Chien Chen; Yu-Wei Chang; Liang-Gee Chen (SoCC, 2007)

Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC. - Tung-Chien Chen; Yu-Han Chen; Sung-Fang Tsai; Shao-Yi Chien; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2007)

Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC. - Tung-Chien Chen; Chuan-Yung Tsai; Yu-Wen Huang; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2007)

A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB Tansmitter. - Moo Sung Chae; Wentai Liu; Zhi Yang; Tung-Chien Chen; Jungsuk Kim; Mohanasankar Sivaprakasam; Mehmet R. Yuce (ISSCC, 2008)

VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC. - Yi-Hau Chen; Tung-Chien Chen; Shao-Yi Chien; Yu-Wen Huang; Liang-Gee Chen (J. Signal Process. Syst., 2008)

Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder. - Yu-Han Chen; Tung-Chien Chen; Chuan-Yung Tsai; Sung-Fang Tsai; Liang-Gee Chen (J. Signal Process. Syst., 2008)

Closed-loop Eyelid Reanimation System with Real-time Blink Detection and Electrochemical Stimulation for Facial Nerve Paralysis. - Kuanfu Chen; Tung-Chien Chen; Kimberly Cockerham; Wentai Liu (ISCAS, 2009)

On-chip Principal Component Analysis with a Mean Pre-estimation Method for Spike Sorting. - Tung-Chien Chen; Kuanfu Chen; Wentai Liu; Liang-Gee Chen (ISCAS, 2009)

128-channel Spike Sorting Processor with a Parallel-folding Structure in 90nm Process. - Tung-Chien Chen; Wentai Liu; Liang-Gee Chen (ISCAS, 2009)

A biomedical multiprocessor SoC for closed-loop neuroprosthetic applications. - Tung-Chien Chen; Kuanfu Chen; Zhi Yang; Kimberly Cockerham; Wentai Liu (ISSCC, 2009)

A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications. - Li-Fu Ding; Wei-Yin Chen; Pei-Kuei Tsung; Tzu-Der Chuang; Hsu-Kuang Chiu; Yu-Han Chen; Pai-Heng Hsiao; Shao-Yi Chien; Tung-Chien Chen; Ping-Chih Lin; Chia-Yu Chang; Liang-Gee Chen (ISSCC, 2009)

Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices. - Yu-Han Chen; Tung-Chien Chen; Chuan-Yung Tsai; Sung-Fang Tsai; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2009)

Accuracy and power tradeoff in spike sorting microsystems with cubic spline interpolation. - Yun-Yu Chen; Tung-Chien Chen; Liang-Gee Chen (ISCAS, 2010)

Sub-microwatt correlation integral processor for implantable closed-loop epileptic neuromodulator. - Yu-Hsin Chen; Tung-Chien Chen; Tsung-Hsueh Lee; Liang-Gee Chen (ISCAS, 2010)

Cubic spline interpolation with overlapped window and data reuse for on-line Hilbert Huang transform biomedical microprocessor. - Nai-Fu Chang; Cheng-Yi Chiang; Tung-Chien Chen; Liang-Gee Chen (EMBC, 2011)

Robust heart rate measurement with phonocardiogram by on-line template extraction and matching. - Yu-Hsin Chen; Hong-Hui Chen; Tung-Chien Chen; Liang-Gee Chen (EMBC, 2011)

Mobile energy expenditure tracking system based on heart rate and motion providing extra extensions for personalized care. - Hong-Hui Chen; Yu-Hsin Chen; Tung-Chien Chen; Liang-Gee Chen (EMBC, 2011)

Seizure prediction based on classification of EEG synchronization patterns with on-line retraining and post-processing scheme. - Cheng-Yi Chiang; Nai-Fu Chang; Tung-Chien Chen; Hong-Hui Chen; Liang-Gee Chen (EMBC, 2011)

Power estimation scheme for lowpower oriented biomedical SoC extended to very deep submicron technology. - Hong-Hui Chen; Tung-Chien Chen; Cheng-Yi Chiang; Liang-Gee Chen (ICASSP, 2011)

Design and implementation of cubic spline interpolation for spike sorting microsystems. - Tung-Chien Chen; Yun-Yu Chen; Tsung-Chuan Ma; Liang-Gee Chen (ICASSP, 2011)

A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications. - Pei-Kuei Tsung; Pin-Chih Lin; Kuan-Yu Chen; Tzu-Der Chuang; Hsin-Jung Yang; Shao-Yi Chien; Li-Fu Ding; Wei-Yin Chen; Chih-Chi Cheng; Tung-Chien Chen; Liang-Gee Chen (ISSCC, 2011)

Analysis and Design of On-sensor ECG Processors for Realtime Detection of Cardiac Anomalies Including VF, VT, and PVC. - Hong-Hui Chen; Cheng-Yi Chiang; Tung-Chien Chen; Chien-Sheng Liu; Yu-Jie Huang; Shey-Shi Lu; Chii-Wann Lin; Liang-Gee Chen (J. Signal Process. Syst., 2011)

Channel selection for epilepsy seizure prediction method based on machine learning. - Nai-Fu Chang; Tung-Chien Chen; Cheng-Yi Chiang; Liang-Gee Chen (EMBC, 2012)

Assessing normality of heart sound by matching pursuit residue with frequency-domain-based templates. - Hong-Hui Chen; Tung-Chien Chen; Liang-Gee Chen (EMBC, 2012)

Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90nm CMOS process. - Tung-Chien Chen; Tsung-Chuan Ma; Yun-Yu Chen; Liang-Gee Chen (EMBC, 2012)

Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events. - Li-Fang Cheng; Tung-Chien Chen; Liang-Gee Chen (EMBC, 2012)

Exploration of reusing the pre-recorded training data set to improve the supervised classifier for EEG-based motor-imagery brain computer interfaces. - Yun-Yu Chen; Tung-Chien Chen; Chien-Chung Chen; Hsin-I Liao; Luk-Ting Sio; Liang-Gee Chen (ISCAS, 2012)

Low-power multi-processor system architecture design for universal biomedical signal processing. - Li-Fang Cheng; Tung-Chien Chen; Liang-Gee Chen (ISCAS, 2013)

Brain-Inspired Framework for Fusion of Multiple Depth Cues. - Chung-Te Li; Yen-Chieh Lai; Chien Wu; Sung-Fang Tsai; Tung-Chien Chen; Shao-Yi Chien; Liang-Gee Chen (IEEE Trans. Circuits Syst. Video Technol., 2013)

Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem. - Tsung-Chuan Ma; Tung-Chien Chen; Liang-Gee Chen (ICASSP, 2014)

A 473 μW wireless 16-channel neural recording SoC with RF energy harvester. - Kun-Ying Yeh; Yu-Jie Huang; Tung-Chien Chen; Liang-Gee Chen; Shey-Shi Lu (VLSI-DAT, 2018)

NeuroPilot: A Cross-Platform Framework for Edge-AI. - Tung-Chien Chen; Wei-Ting Wang; Kloze Kao; Chia-Lin Yu; Code Lin; Shu-Hsin Chang; Pei-Kuei Tsung (AICAS, 2019)

Heterogeneous Computing for Edge AI. - Pei-Kuei Tsung; Tung-Chien Chen; Chien-Hung Lin; Chih-Yu Chang; Jih-Ming Hsu (VLSI-DAT, 2019)